MULTIPLE-COMPONENT MEMORY INTERFACE SYSTEM AND METHOD

• US 20080028135A1
• Filed: 07/31/2006
• Published: 01/31/2008
• Est. Priority Date: 07/31/2006
• Status: Abandoned Application

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Application Number:
  US11/461,441
• Publication Number:
  US 20080028135A1
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method are provided, wherein a first component and a second component are operable to interface a plurality of memory circuits and a system.

Claims

1. A sub-system, comprising:

a first component and a second component operable to interface a plurality of memory circuits and a system.

2. The sub-system of claim 1, wherein at least one of the first component and the second component is operable to simulate at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits.

3. The sub-system of claim 2, wherein the at least on aspect includes a signal.

4. The sub-system of claim 3, wherein at least one of the first component and the second component is operable to delay the signal.

5. The sub-system of claim 2, wherein the at least one aspect includes a memory capacity.

6. The sub-system of claim 2, wherein the at least on aspect includes a timing.

7. The sub-system of claim 6, wherein the timing relates to a latency.

8. The sub-system of claim 1, wherein at least one of the first component and the second component is operable to perform a power savings operation.

9. The sub-system of claim 1, wherein at least one of the first component and the second component is operable to perform a refresh operation.

10. The sub-system of claim 1, wherein at least one of the first component and the second component is operable to simulate at least one memory circuit with a first memory capacity that is greater than a second memory capacity of at least one of the plurality of memory circuits.

11. The sub-system of claim 1, wherein at least one of the first component and the second component is operable to receive first information in association with a first operation to be performed on at least one of the plurality of memory circuits, receiving second information in association with a second operation to be performed on at least one of the plurality of memory circuits, and performing the second operation utilizing the portion of the first information in addition to the second information.

12. The sub-system of claim 1, wherein the first component and the second component share interface tasks.

13. The sub-system of claim 1, wherein the first component and the second component perform different interface tasks.

14. The sub-system of claim 1, wherein the first component or the second component includes an interface circuit.

15. The sub-system of claim 1, wherein the first component or the second component includes an advanced memory buffer (AMB).

16. The sub-system of claim 1, wherein the first component or the second component includes a circuit that is positioned on a dual in-line memory module (DIMM).

17. The sub-system of claim 1, wherein the first component or the second component includes a memory controller.

18. The sub-system of claim 1, wherein the first component or the second component includes a register.

19. A method, comprising:

interfacing a system utilizing a first component; and

interfacing the first component and a plurality of memory circuits, utilizing a second component.

20. A system, comprising:

a first component operable to interface a system;

a second component operable to interface the first component and a plurality of memory circuits;

wherein the first component and the second component share interface tasks.