METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES
First Claim
Patent Images
1. An interface circuit configured to manage refresh command sequences, the interface circuit comprising:
- a system interface adapted to receive a refresh command from a memory controller;
a means for determining the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller; and
at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices.
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Abstract
One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices
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Citations
22 Claims
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1. An interface circuit configured to manage refresh command sequences, the interface circuit comprising:
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a system interface adapted to receive a refresh command from a memory controller;
a means for determining the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller; and
at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification