Method and Apparatus For Refresh Management of Memory Modules
First Claim
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1. A method for generating staggered refresh commands for two or more memory devices, the method comprising:
- analyzing a connectivity for transmitting refresh signals between an interface circuit and the two or more memory devices;
calculating a timing for issuing staggered refresh command to the two or more memory devices based on a refresh command received from a memory controller and the analyzed connectivity; and
asserting the staggered refresh commands to the two or more memory devices at the calculated times.
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Abstract
One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices
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Citations
30 Claims
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1. A method for generating staggered refresh commands for two or more memory devices, the method comprising:
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analyzing a connectivity for transmitting refresh signals between an interface circuit and the two or more memory devices; calculating a timing for issuing staggered refresh command to the two or more memory devices based on a refresh command received from a memory controller and the analyzed connectivity; and asserting the staggered refresh commands to the two or more memory devices at the calculated times. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A computer-readable medium including instructions that when executed by a processing unit cause the processing unit to generate staggered refresh commands for two or more memory devices, by performing the steps of:
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analyzing a connectivity for transmitting refresh signals between an interface circuit and the two or more memory devices; calculating a timing for issuing staggered refresh command to the two or more memory devices based on a refresh command received from a memory controller and the analyzed connectivity; and asserting the staggered refresh commands to the two or more memory devices at the calculated times. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification