Integrated memory device and method of operating a memory device
First Claim
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1. An integrated memory device comprising:
- a memory core having a plurality of memory cells;
a group of terminals for communication between the memory device and an external electronic device;
a data buffer for temporary storage of data, the data buffer being coupled to the group of terminals and to the memory core, the data buffer comprising a plurality of data buffer sections, each data buffer section being capable of temporarily storing at least one data frame and being accessible by a respective data buffer address; and
a data buffer control unit;
wherein the memory device is constructed to generate, for each data buffer section, at least one data bit assigned to the respective data buffer section, the data bit indicating whether the respective data buffer section comprises empty data buffer area for storing at least one data frame or whether the respective data buffer section is occupied; and
wherein the data buffer control unit is constructed to calculate, using the data bits assigned to the data buffer sections, a data buffer address of a data buffer section to which data frames are transmitted for being stored temporarily.
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Abstract
An integrated memory device includes a memory core having a plurality of memory cells and a group of terminals for communication between the memory device and an external electronic device. A data buffer temporarily stores data. The data buffer is coupled to the group of terminals and to the memory core. The data buffer includes a plurality of data buffer sections. Each data buffer section is capable of temporarily storing at least one data frame and being accessible by a respective data buffer address. A data buffer control unit is also provided.
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Citations
58 Claims
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1. An integrated memory device comprising:
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a memory core having a plurality of memory cells; a group of terminals for communication between the memory device and an external electronic device; a data buffer for temporary storage of data, the data buffer being coupled to the group of terminals and to the memory core, the data buffer comprising a plurality of data buffer sections, each data buffer section being capable of temporarily storing at least one data frame and being accessible by a respective data buffer address; and a data buffer control unit; wherein the memory device is constructed to generate, for each data buffer section, at least one data bit assigned to the respective data buffer section, the data bit indicating whether the respective data buffer section comprises empty data buffer area for storing at least one data frame or whether the respective data buffer section is occupied; and wherein the data buffer control unit is constructed to calculate, using the data bits assigned to the data buffer sections, a data buffer address of a data buffer section to which data frames are transmitted for being stored temporarily. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A method of operating a memory device comprising a data buffer having a plurality of data buffer sections accessible by data buffer addresses, the method comprising:
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assigning to each data buffer section a data buffer address, the data buffer addresses being represented by data buffer address numbers and the data buffer address numbers of the data buffer sections constituting a predefined order of data buffer address numbers; generating for each data buffer section at least one data bit assigned to the respective data buffer section, the data bits indicating whether the respective data buffer section comprises empty data buffer area for storing at least one data frame or whether the respective data buffer section is occupied; and combining the data bits with one another, thereby calculating a data buffer address number that represents, within the predefined order of data buffer address numbers, a first data buffer address number corresponding to a data buffer section that comprises empty data buffer area for storing at least one data frame. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
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Specification