FPGA Co-Processor For Accelerated Computation

• US 20080028186A1
• Filed: 07/27/2007
• Published: 01/31/2008
• Est. Priority Date: 07/28/2006
• Status: Active Grant

• Current Assignee: DRC Computer
• Original Assignee: DRC Computer
• Inventors: Casselman, Steven
• Granted Patent: US 7,856,545 B2
• Time in Patent Office: Days
• US Class Current: 712/37
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H05K 1/0286 Programmable, customizable or modifiable circuits by programmable non-printed jumper connections H05K3/222
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/10212 Programmable component
• CPC Class Codes: H05K 2201/10325 Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A co-processor module for accelerating computational performance includes a Field Programmable Gate Array (“FPGA”) and a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA. A non-volatile memory is coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA. A mechanical and electrical interface is for being plugged into a microprocessor socket of a motherboard for direct communication with at least one microprocessor capable of being coupled to the motherboard. After completion of a start-up cycle, the FPGA is configured for direct communication with the at least one microprocessor via a microprocessor bus to which the microprocessor socket is coupled.

Claims

1. An accelerator module, comprising:

a Field Programmable Gate Array (“

FPGA”

)

a Programmable Logic Device (“

PLD”

) coupled to the FPGA and configured to control start-up configuration of the FPGA;

a non-volatile memory coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA; and

a mechanical and electrical interface for being plugged into a microprocessor socket of a motherboard for direct communication with at least one microprocessor capable of being coupled to the motherboard;

the FPGA after completion of a start-up cycle being configured for direct communication with the at least one microprocessor via a microprocessor bus to which the microprocessor socket is coupled.

2. The accelerator module according to claim 1, wherein the microprocessor bus is a point-to-point bus.

3. The accelerator module according to claim 2, wherein the FPGA after completion of the start-up cycle is configured for direct communication with resources associated with the motherboard in addition to the at least one microprocessor, wherein the resources are directly accessible by the FPGA via the point-to-point bus, the point-to-point bus being a Hypertransport bus.

4. The accelerator module according to claim 3, wherein the FPGA after completion of the start-up cycle is further configured for direct communication via a dedicated bus with dynamic random access memory forming a portion of the resources associated with the motherboard.

5. The accelerator module according to claim 2, wherein the FPGA after completion of the start-up cycle is further configured for direct communication with resources associated with the motherboard in addition to the at least one microprocessor, wherein the resources include random access memory which is directly accessible by the FPGA via a dedicated memory bus.

6. The accelerator module according to claim 5, wherein the random access memory is Dynamic Random Access. Memory (“

DRAM”

).

7. The accelerator module according to claim 1, wherein the FPGA after completion of the start-up cycle is configured for direct communication with system memory coupled to the motherboard which is associated with the microprocessor point-to-point bus to which the microprocessor socket is coupled.

8. The accelerator module according to claim 1, further comprising Static Random Access Memory (“

SRAM”

) coupled to the FPGA and configured for storing configuration information for configuring at least a user programmable logic portion of the FPGA.

9. A method for co-processing, comprising:

coupling an accelerator module to a microprocessor bus, the accelerator module including a Field Programmable Gate Array (“

FPGA”

);

loading a microprocessor bus interface bitstream into the FPGA to program programmable logic thereof,

transferring data to first memory of the accelerator module via a microprocessor bus using a microprocessor bus interface instantiated in the FPGA responsive to the microprocessor bus interface bitstream; and

instantiating a default configuration bitstream stored in the first memory in the FPGA to configure the FPGA to have the microprocessor bus interface with sufficient functionality to be recognized by a microprocessor coupled to the microprocessor bus.

10. The method according to claim 9, wherein the loading is via a JTAG interface of the FPGA.

11. The method according to claim 10, wherein the loading and the transferring are under control of a Programmable Logic Device (“

PLD”

), the PLD being included as part of the accelerator module.

12. The method according to claim 9, further comprising:

communicating under control of the microprocessor a configuration pattern to second memory of the accelerator module using a first memory interface instantiated in the FPGA responsive to the instantiating of the default configuration bitstream.

13. The method according to claim 12, further comprising sending control information from the microprocessor to the FPGA to indicate location of the configuration pattern in the second memory for instantiation in user programmable logic of the FPGA.

14. The method according to claim 13, wherein the control information is for partial reconfiguration of the user programmable logic of the FPGA.

15. The method according to claim 14, wherein the first memory is flash memory;

and wherein the second memory is either Static Random Access Memory (“

SRAM”

) or Dynamic Random Access Memory (“

DRAM”

).

16. The method according to claim 9, further comprising communicating under control of the microprocessor a configuration pattern to second memory under control of a Programmable Logic Device (“

PLD”

), the PLD being included as part of the accelerator module.

17. The method according to claim 16, further comprising sending control information from the microprocessor to the PLD to indicate location of the configuration pattern in the second memory for instantiation in user programmable logic of the FPGA.

18. The method according to claim 17, wherein the control information is for full reconfiguration of at least the user programmable logic of the FPGA.

19. The method according to claim 18, wherein the first memory is flash memory;

and wherein the second memory is Static Random Access Memory (“

SRAM”

).

20. The method according to claim 9, wherein the microprocessor bus interface bitstream and the default configuration bitstream are instantiated in the FPGA with pre-assigned fixed placement.

21. A method for co-processing, comprising:

coupling an accelerator module to a microprocessor bus, the accelerator module including a Field Programmable Gate Array (“

FPGA”

) and first memory, the first memory having a default configuration bitstream stored therein;

loading the default configuration bitstream into the FPGA to program programmable logic thereof, the default configuration bitstream including a microprocessor bus interface; and

configuring the FPGA with the default configuration bitstream with sufficient functionality to be recognized by a microprocessor coupled to the microprocessor bus.

22. The method according to claim 21, wherein the loading is via a JTAG interface of the FPGA.

23. The method according to claim 22, wherein the loading is under control of a Programmable Logic Device (“

PLD”

) included as part of the accelerator module.

24. The method according to claim 21, further comprising, communicating under control of the microprocessor a configuration pattern to second memory using a first memory interface instantiated in the FPGA responsive to the configuring of the FPGA with the default configuration bitstream.

25. The method according to claim 24, further comprising sending control information from the microprocessor to the FPGA to indicate location of the configuration pattern in the second memory for instantiation in user programmable logic of the FPGA.

26. The method according to claim 25, wherein the control information is for partial reconfiguration of the user programmable logic of the FPGA.

27. The method according to claim 26, wherein the first memory is flash memory;

and wherein the second memory is either Static Random Access Memory (“

SRAM”

) or Dynamic Random Access Memory (“

DRAM”

).

28. The method according to claim 21, further comprising communicating under control of the microprocessor a configuration pattern to second memory under control of a Programmable Logic Device (“

PLD”

), the PLD being included as part of the accelerator module.

29. The method according to claim 28, further comprising sending control information from the microprocessor to the PLD to indicate location of the configuration pattern in the second memory for instantiation in user programmable logic of the FPGA.

30. The method according to claim 29, wherein the control information is for full reconfiguration of at least the user programmable logic of the FPGA.

31. The method according to claim 30, wherein the first memory is flash memory;

and wherein the second memory is Static Random Access Memory (“

SRAM”

).

32. The method according to claim 21, wherein the default configuration bitstream is instantiated in the FPGA with pre-assigned fixed placement.

33. An accelerator system, comprising:

a first motherboard having accelerator modules;

a second motherboard having at least one microprocessor;

each of the accelerator modules including;

a Field Programmable Gate Array (“

FPGA”

)

a Programmable Logic Device (“

PLD”

) coupled to the FPGA and configured to control start-up configuration of the FPGA;

a non-volatile memory coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA; and

a mechanical and electrical interface configured for being plugged into a microprocessor socket of the first motherboard for direct communication as between the accelerator modules;

the microprocessor socket being coupled to a microprocessor bus for the direct communication between the accelerator modules.

34. The accelerator system according to claim 33, wherein the microprocessor bus is a point-to-point bus.

35. The accelerator system according to claim 34, wherein the microprocessor bus is a Hypertransport bus.