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FPGA Co-Processor For Accelerated Computation

  • US 20080028186A1
  • Filed: 07/27/2007
  • Published: 01/31/2008
  • Est. Priority Date: 07/28/2006
  • Status: Active Grant
First Claim
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1. An accelerator module, comprising:

  • a Field Programmable Gate Array (“

    FPGA”

    ) a Programmable Logic Device (“

    PLD”

    ) coupled to the FPGA and configured to control start-up configuration of the FPGA;

    a non-volatile memory coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA; and

    a mechanical and electrical interface for being plugged into a microprocessor socket of a motherboard for direct communication with at least one microprocessor capable of being coupled to the motherboard;

    the FPGA after completion of a start-up cycle being configured for direct communication with the at least one microprocessor via a microprocessor bus to which the microprocessor socket is coupled.

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