Semiconductor buffer architecture for III-V devices on silicon substrates

• US 20080029756A1
• Filed: 08/02/2006
• Published: 02/07/2008
• Est. Priority Date: 08/02/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hudait, Mantu K., Loubychev, Dmitri, Fastenau, Joel M., Shaheen, Mohamad A., Liu, Amy W.K.
• Granted Patent: US 7,851,780 B2
• Time in Patent Office: Days
• US Class Current: 257/14
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02466 Antimonides
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02549 Antimonides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802

Abstract

A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×10⁸ cm⁻² to be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.

Claims

1. An apparatus comprising:

a silicon substrate;

a buffer on the silicon substrate, wherein the buffer includes a GaSb layer in contact with the silicon substrate; and

a compound semiconductor device layer on the buffer.

2. The apparatus of claim 1, wherein the GaSb layer is on a (100) surface of the silicon substrate that is offcut 2 to 12 degrees in the [110] direction.

3. The apparatus of claim 1, wherein the metamorphic buffer further includes an isolative semiconductor layer disposed between the GaSb layer and said compound semiconductor device layer.

4. The apparatus of claim 3, wherein the isolative semiconductor layer has a resistivity on the order of 1×

10⁷ ohm-cm.

5. The apparatus of claim 3, wherein the isolative semiconductor layer comprises AlSb.

6. The apparatus of claim 5, wherein the isolative semiconductor layer comprises Al_xGa_1-xSb, wherein x is between approximately 0.1 and 1.0.

7. The apparatus of claim 1, wherein the compound semiconductor device layer comprises InSb.

8. The apparatus of claim 1, further comprising a device formed in the compound semiconductor device layer, wherein the device is selected from the group comprising:

an electronic device, an optical device, an electro-optical device.

9. The apparatus of claim 8, wherein the electronic device formed in the compound semiconductor is a quantum well transistor.

10. A method of forming a compound semiconductor device layer on a silicon substrate comprising:

forming a buffer on the off-cut surface of the silicon substrate, wherein the buffer comprises a GaSb layer substantially free of anti-phase domains in contact with the offcut silicon surface;

forming a compound semiconductor device layer on the buffer layer.

11. The method of claim 10, further comprising off-cutting a (100) surface of the silicon substrate in the [110] direction by approximately 2 to 12 degrees.

12. The method of claim 10, further comprising off-cutting the silicon substrate along a higher order plane selected from the group consisting of:

(211), (511), (711), (013).

13. The method of claim 10, wherein forming the compound semiconductor device layer upon the buffer further comprises depositing InSb at a growth temperature between approximately 300C and 500C.

14. The method of claim 10, wherein forming the GaSb layer further comprises:

depositing GaSb upon the surface of the silicon substrate at a first growth temperature and first growth rate to form a GaSb nucleation layer; and

depositing GaSb upon the GaSb nucleation layer at a second growth temperature and second growth rate to thicken the buffer, wherein the second growth temperature is higher than the first growth temperature.

15. The method of claim 14 wherein the nucleation layer is formed by molecular beam epitaxy (MBE) at the first growth rate of approximately 1 um/hr.

16. The method of claim 15 wherein the first temperature is between approximately 300C and 600C.

17. The method of claim 14, wherein the nucleation layer is formed by migration enhanced epitaxy (MEE) at the first growth rate of approximately 0.1 um/hr.

18. The method of claim 17, wherein the first temperature is between approximately 400C and 650C.

19. The method of claim 14, wherein forming the buffer further comprises:

forming an isolative semiconductor layer upon the GaSb layer, wherein the isolative semiconductor layer comprises a material having a bandgap greater than approximately 1.4 eV.

20. The method of claim 19, wherein forming the isolative semiconductor layer further comprises:

depositing the isolative semiconductor material upon the GaSb layer at a third growth temperature that is equal to or below the highest GaSb layer growth temperature to form a transition layer; and

depositing the isolative semiconductor material upon the transition layer at a fourth growth temperature that is greater than the third growth temperature to increase the thickness of the isolative layer.

21. The method of claim 19, wherein the transition layer is grown to a thickness between approximately 0.05 um and 0.2 um.

22. The method of claim 19, wherein the third growth temperature is between approximately 500C and 700C.

23. The method of claim 19, wherein the fourth growth temperature is higher than the highest growth temperature used to form the GaSb layer.

24. A method of forming a compound semiconductor device layer on a silicon substrate comprising:

off-cutting a (100) surface of the silicon substrate in the [110] direction by approximately 2 to 12 degrees;

depositing GaSb upon the off-cut surface of the silicon substrate at a first growth temperature and first growth rate to form a GaSb nucleation layer;

depositing GaSb upon the GaSb nucleation layer at a second growth temperature and second growth rate to thicken the buffer, wherein the second growth temperature is higher than the first growth temperature;

depositing an isolative semiconductor material upon the GaSb layer at a third growth temperature that is equal to or below the highest GaSb layer growth temperature to form a transition layer;

depositing the isolative semiconductor material upon the transition layer at a fourth growth temperature that is greater than the third growth temperature to increase the thickness of the isolative layer;

depositing a device layer including a quantum well layer disposed between two barrier layers, wherein the barrier layers have a larger bandgap than the quantum well layer; and

forming a quantum well transistor in the device layer.

25. The method of claim 24, wherein the isolative semiconductor material comprises a material selected from the group comprising:

AlSb and Al_xGa_1-xSb, wherein x is between approximately 0.1 and 1.0.