POST VERTICAL INTERCONNECTS FORMED WITH SILICIDE ETCH STOP AND METHOD OF MAKING
First Claim
1. A plurality of active elements comprising:
- active elements having a minimum feature size less than about 0.25 micron; and
at least one vertical interconnect having a smallest patterned dimension substantially the same as the minimum feature size.
3 Assignments
0 Petitions
Accused Products
Abstract
A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the etch stop layer. The layer of contact material is patterned to form posts. Dielectric is deposited over and between the posts, then the dielectric planarized to expose the tops of the posts. The posts can serve as vertical interconnects which electrically connect a next conductive layer formed on and in contact with the vertical interconnects with the underlying etch stop layer. The patterned dimension of vertical interconnects formed according to the present disclosure can be substantially the same as the minimum feature size, even at very small minimum feature size.
22 Citations
25 Claims
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1. A plurality of active elements comprising:
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active elements having a minimum feature size less than about 0.25 micron; and
at least one vertical interconnect having a smallest patterned dimension substantially the same as the minimum feature size. - View Dependent Claims (2, 3, 4)
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5. A plurality of active elements comprising:
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active elements having a minimum feature size; and
at least one vertical interconnect, the interconnect having a smallest patterned dimension, formed by a method comprising;
forming an etch stop layer comprising cobalt silicide or nickel silicide;
forming a layer of contact material in contact with the etch stop layer;
patterning and etching the contact material to form the vertical interconnect, wherein the etching of the patterning and etching step stops on the etch stop layer; and
forming metal silicide above and in contact with the vertical interconnect, wherein the smallest patterned dimension of the vertical interconnect is substantially the same as the minimum feature size. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A monolithic three dimensional memory array comprising first and second memory levels, and further comprising first vertical interconnects, the first interconnects formed by a method comprising:
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forming a first etch stop layer;
forming a first contact layer;
patterning and etching the first contact layer to form the first vertical interconnects, wherein the first etch stop layer acts as an etch stop; and
forming metal silicide above and in contact with the first vertical interconnects. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A memory array comprising:
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a plurality of first array lines extending in a first direction;
a plurality of second array lines extending in a second direction substantially perpendicular to the first direction; and
a plurality of vertical interconnects formed in a fan-out area, wherein each vertical interconnect comprises contact material and is formed on or in contact with an etch stop layer. - View Dependent Claims (23)
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24. A memory array comprising:
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a plurality of first array lines extending in a first direction;
a plurality of second array lines extending in a second direction substantially perpendicular to the first direction; and
a plurality of vertical interconnects formed in a fan-out area, wherein each vertical interconnect is patterned and etched as a positive feature, the etch stopping on an etch stop layer. - View Dependent Claims (25)
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Specification