MULTI-CHANNEL, MULTI-POWER CLASS D AMPLIFIER WITH REGULATED POWER SUPPLY

• US 20080030268A1
• Filed: 10/08/2007
• Published: 02/07/2008
• Est. Priority Date: 01/12/2005
• Status: Abandoned Application

• Current Assignee: Patrick Quilter
• Original Assignee: Patrick Quilter
• Inventors: Quilter, Patrick
• Application Number:
  US11/868,896
• Publication Number:
  US 20080030268A1
• Time in Patent Office: Days
• US Class Current: 330/10
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 2200/03 the amplifier being designed for audio applications
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers

Abstract

Methods and apparatus are disclosed to reduce the size, weight, and heat loss of power modules mountable in loudspeakers. Disclosed embodiments replace conventional linear technology with high frequency switching technology in both the power supply and amplifier. In these embodiments Class-D switching occurs at a low and fixed frequency, using standard components, with audio performance improvements through adaptation of internal error correction. By permitting 100% modulation, maximum output power is obtained, and a simple clip-detecting scheme is possible. A half-bridge and full-bridge with a single main supply reservoir is disclosed, obtaining useful allocation of output power while enabling the use of a simplified power supply. Power supply improvements include simplification and high efficiency, while meeting the particular system requirements of this scheme. Advantages include: increased acoustic output, reduced distortion, wider frequency range, smaller and lighter speaker housings, and lower cost.

Claims

1-25. -25. (canceled)

26. A Class-D audio power amplification method using a low-frequency driver using a full-bridge and a high-frequency driver using a half-bridge, the method comprising:

generating a flat-topped rectangular switching waveform whose peak-to-peak value is maintained at a regulated level; and

maintaining a voltage on at least one secondary capacitor reservoir by passing the generated waveform through a high frequency isolation transformer, with one or more secondary windings whose outputs are peak-to-peak rectified, wherein each secondary rectifies one square-wave voltage substantially undisturbed by loading of other secondaries.

27. A power conversion system configured to perform envelope-rectification wherein a regulated peak-to-peak voltage maintains a voltage on one or more isolated DC reservoirs without using inductance, and configured to perform active-clamping wherein the regulated peak-to-peak voltage and a constrained high-low duty cycle produces a constantly-running primary switching waveform, the power converter comprising:

a high frequency isolation transformer and wherein a first end of the transformer primary winding is coupled to an off-line DC reservoir;

a first switching transistor configured to couple a second end of the transformer primary winding to a low end of the DC reservoir;

a second reservoir clamping the primary winding voltage and establishing a boost voltage, maintainable at a set voltage by varying an on/off ratio of the first switching transistor; and

a shunt capacitance of sufficient amount, placed across the transformer primary, such that an inductive current stored at the end of each switching period is sufficient to produce a transition to an opposite rail.

28. The power conversion system of claim 27, wherein active-clamping is implemented by a second switching transistor that is controlled in alternation with the first switching transistor.

29. The power conversion system of claim 27, wherein the active clamping is controlled such that:

the first switch is turned off and the primary winding voltage goes to the boost reservoir voltage, whereupon clamping current flows backwards through an intrinsic diode of the second switch into the boost reservoir;

the second switch is turned on after a short period and assumes a bi-directional low-resistance state, wherein the boost reservoir voltage climbs as the leakage energy is discharged into the reservoir and the reservoir voltage exceeds the voltage reflected back from the secondary winding, as clamped by the secondary winding rectifiers into the secondary reservoirs;

the boost reservoir is discharged until it matches the reflected output voltage, while adding to the energy reaching the load, wherein the voltage of the boost reservoir tracks the output voltage;

the second switch is turned off when the current in the primary shunt inductor is reversed and the primary voltage is carried back to zero; and

the first switch is turned on to begin a next cycle.

30. The power conversion system of claim 27, wherein the voltage of the boost reservoir is used as a primary-side reference voltage for a regulator control system.

31. A power conversion method comprising:

coupling a first end of an isolation transformer primary winding to a DC reservoir;

sustaining substantial DC current in the primary;

reducing series inductance;

ramping up the primary winding current by configuring a first switching transistor to couple a second end of the isolation transformer primary winding to a low end of the DC reservoir;

increasing the primary winding voltage to a level higher than the DC reservoir by turning off the first switching transistor after a predetermined interval;

establishing a boost-voltage, which is maintained at a set voltage by varying an on/off ratio of the first switching transistor, by clamping the voltage to a second reservoir;

producing a peak-to-peak voltage by obtaining a desired rectangular on-off waveform constrained between the low side of the DC reservoir and the boost voltage of the second reservoir;

maintaining predictable voltages on one or more isolated secondary capacitors by rectifying the voltage waveform, which is coupled through transformer windings on the secondary side; and

performing gradual switching transitions by producing a transition to an opposite rail with a dv/dt in a shunt capacitance across the transformer primary, wherein dv/dt is caused by an inductive current stored at the end of each switching period.

32. The method of claim 31, wherein the current through the shunt capacitor is rectified and used to power a controller circuitry.

33. The method of claim 31, wherein the off-line voltage and boost voltage remain within about 4:

1 ratio such that the high-low ratio of the switching waveform remains within these limits and peak currents remain reasonable.

34. The method of claim 31, wherein the rectified offline voltage is filtered and the boost converter is operated in such a manner as to perform active power factor correction of the currents from the AC mains.

35. A clocked audio amplification method comprising:

synchronizing at least a part of the processes by a system clock signal;

forming a triangular signal from the clock signal;

pulse-width modulating (PWM) the triangular signal, by a high speed comparator, into a variable duty cycle square signal, using an audio input signal;

integrating the modulated pulses;

holding the amplifier in a muting state for a predetermined period wherein switching is disabled;

raising an output voltage gradually to an operating point during the holding period;

resuming switching after the holding period;

feeding back a half-bridge output to an amplifier input;

feeding back from the switched output to the integrator;

decoupling the average DC voltage of the clock signal;

decoupling DC content of the output feedback;

decoupling any DC offset from the audio input section; and

maintaining the average voltage at ground;

wherein the DC voltage of the comparator input stands substantially at zero, and the PWM signal averages substantially 50% on/off at idle, with excursions from 0 to 100% as driven by the audio input signal, and wherein the substantially 50% idle condition substantially centers the switched waveform between ground and +Vcc.

36. The audio amplification method of claim 35, wherein, for amplifiers that are allowed to reach full modulation, clipping is detected and a user is alerted that the rated power has been exceeded.

37. The audio amplification method of claim 35, wherein overcurrent signals are fed back to a global feedback node and wherein an overcurrent flag is delivered to a muting control block that delivers a muting signal after a pre-determined interval.

38. The audio amplification method of claim 35, wherein switching may start and stop without appreciable transients by causing output switch transitions to occur halfway through each clock pulse.