System and method for power management in memory systems

• US 20080031030A1
• Filed: 09/20/2006
• Published: 02/07/2008
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Granted Patent: US 7,590,796 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2272 Latency related aspects
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.

Claims

1. A sub-system, comprising:

an interface circuit in communication with a plurality of physical memory circuits and a system, the interface circuit operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.

2. The sub-system of claim 1, wherein the at least one virtual memory circuit includes a single virtual memory circuit.

3. The sub-system of claim 1, wherein the interface circuit includes a circuit that is positioned on a dual in-line memory module (DIMM).

4. The sub-system of claim 1, wherein the interface circuit is selected from the group consisting of a buffer, a register, a memory controller, and an advanced memory buffer (AMB).

5. The sub-system of claim 1, wherein the simulating is performed utilizing a power management operation.

6. The sub-system of claim 5, wherein the power management operation includes a power saving operation.

7. The sub-system of claim 6, wherein the power saving operation includes a power down operation.

8. The sub-system of claim 6, wherein the power saving operation involves at least one of a clock enable signal and a chip select signal.

9. The sub-system of claim 6, wherein at least a portion of the physical memory circuits is subject to the power saving operation.

10. The sub-system of claim 9, wherein the power saving operation includes powering down a first portion of the physical memory circuits while a second portion of the physical memory circuits is subject to commands.

11. The sub-system of claim 9, wherein the power saving operation includes powering down one or more of the physical memory circuits based on at least one state of one or more of the physical memory circuits.

12. The sub-system of claim 11, wherein the at least one state is selected from the group consisting of a status of the one or more of the physical memory circuits, a predetermined combination of commands issued to the one or more of the physical memory circuits, a predetermined pattern of commands issued to the one or more of the physical memory circuits, and a predetermined absence of commands issued to the one or more of the physical memory circuits.

13. The sub-system of claim 1, wherein the simulating is performed utilizing a delay.

14. The sub-system of claim 1, wherein the simulating of the first power behavior results in a first power consumption associated with the at least one virtual memory circuit that is different from a second power consumption of the physical memory circuits.

15. The sub-system of claim 14, wherein the first power consumption is less than the second power consumption.

16. The sub-system of claim 1, wherein the interface circuit and the physical memory circuits take the form of a stack.

17. The sub-system of claim 16, wherein the stack includes a single interface circuit.

18. The sub-system of claim 16, wherein the stack includes a plurality of interface circuits.

19. A method, comprising:

interfacing a plurality of physical memory circuits and a system; and

simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.

20. A system, comprising:

a plurality of physical memory circuits; and

an interface circuit in communication with the physical memory circuits, the interface circuit operable to interface the physical memory circuits for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.