Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same

• US 20080031048A1
• Filed: 08/06/2007
• Published: 02/07/2008
• Est. Priority Date: 08/04/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ki-Nam, Jung, Soon-Moon, Jeong, Jae-Hun, Cho, Hoo-Sung
• Granted Patent: US 7,701,771 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.

Claims

1. A memory device comprising:

L semiconductor layers stacked, L being an integer greater than 1;

a gate structure on each of the semiconductor layers;

N bitlines on the gate structures and crossing over the gate structures, N being an integer greater than 1; and

a common source line on each of the semiconductor layers, each of the common source lines connected to each other such that the common source lines have equipotentiality with each other.

2. The memory device of claim 1, wherein

each of the gate structures includes a string selection line, a ground selection line, and M wordlines between the string selection line and the ground selection line, M being an integer greater than 1, and

the N bit lines cross over the string selection line, the ground selection line, and the wordlines of each gate structure over the uppermost semiconductor layer.

3. The memory device of claim 2, wherein

each of the semiconductor layers includes at least N active regions in parallel with the bitlines,

each of the active regions includes a source region and a drain region at opposite sides of the gate structure and internal impurity regions between the string and ground selection lines and the wordlines,

the string selection line, the ground selection line, the wordlines, and the common source line cross the active regions in each of the semiconductor layers, and

the source regions at the one side of the gate structure are electrically connected to each other by the common source line on each of the semiconductor layers.

4. The memory device of claim 3, further comprising:

bitline plugs at the other side of the gate structure to electrically connect the bitlines to the drain regions at the other side of the gate structure.

5. The memory device of claim 2, wherein corresponding wordlines disposed on the respective semiconductor layers are connected to each other to have equipotentiality with each other.

6. The memory device of claim 5, wherein programming a memory cell selected by a wordline and a bitline of one of the semiconductor layers comprises:

applying a turn-on voltage and a turn-off voltage to the string selection line and the ground selection line of a selected semiconductor layer, respectively;

applying the turn-off voltage to the string and ground selection lines of unselected semiconductor layers;

applying a program voltage to a selected wordline;

applying a pass voltage to unselected wordlines;

applying a bitline voltage lower than the program voltage to a selected bitline;

applying an unselected bitline voltage higher than the selected bitline voltage and lower than the program voltage to unselected bitlines; and

applying a common source line voltage higher than a ground voltage and lower than a power supply voltage to the common source lines,

wherein corresponding wordlines of the semiconductor layers are connected to an equivalent voltage.

7. The memory device of claim 5, wherein reading a memory cell selected by a wordline and a bitline of one of the semiconductor layers comprises:

applying a read voltage to the string and ground selection lines of a selected semiconductor layer and unselected wordlines;

applying a turn-off voltage to the string and ground selection lines of unselected semiconductor layers;

applying a voltage of 0 volts to a selected wordline; and

applying a precharge voltage to a selected bitline,

wherein corresponding wordlines of the semiconductor layers are connected to an equivalent voltage.

8. The memory device of claim 2, wherein

the string selection lines disposed on the respective semiconductor layers are connected to each other to have equipotentiality with each other;

and

the ground selection lines disposed on the respective semiconductor layers are connected to each other to have equipotentiality with each other.

9. The memory device of claim 8, wherein programming a memory cell selected by a wordline and a bitline of one of the semiconductor layers comprises:

applying a turn-on voltage and a turn-off voltage to each of the string selection lines and each of the ground selection lines, respectively;

applying a program voltage to a selected wordline of a selected semiconductor layer;

applying a pass voltage to unselected wordlines;

applying a selected bitline voltage lower than the program voltage to a selected bitline;

applying an unselected bitline voltage, which is a voltage higher than the selected bitline voltage and lower than the program voltage, to unselected bitlines; and

applying a common source line voltage, which is higher than a ground voltage and lower than a power supply voltage, to the common source lines.

10. The memory device of claim 8, wherein reading a memory cell selected by a wordline and a bitline of one of the semiconductor layer comprises:

applying a read voltage to the string and ground selection lines and unselected wordlines of a selected semiconductor layer;

applying a voltage of 0 volts to a selected wordline; and

applying a voltage of 0 volts to wordlines of an unselected semiconductor layer;

applying a precharge voltage to a selected bitline,

wherein the read voltage is equivalently applied to the string selection lines and the ground selection lines of the selected semiconductor layer.

11. The memory device of claim 2, wherein programming a memory cell selected by a wordline and a bitline of one of the semiconductor layers comprises:

applying a turn-on voltage to the string selection line of a selected semiconductor layer;

applying a turn-off voltage to the ground selection line of the selected semiconductor layer and the string and ground selection lines of unselected semiconductor layers;

applying a program voltage to a selected wordline of the selected semiconductor layer;

applying a pass voltage to unselected wordlines; and

applying a selected bitline voltage, which is lower than the program voltage, to a selected bitline.

12. The memory device of claim 11, wherein programming a memory cell selected by a wordline and a bitline of the semiconductor layer comprises:

applying an unselected bitline voltage, which is higher than the selected bitline voltage and lower than the program voltage, to unselected bitlines; and

applying a common source line voltage, which is higher than a ground voltage and lower than a power supply voltage, to the common source lines.

13. The memory device of claim 12, wherein

the turn-on voltage is the power supply voltage;

the program voltage is between about 10 and 20 volts;

the pass voltage is lower than the program voltage;

the selected bitline voltage is 0 volts; and

the unselected bitline voltage is the power supply voltage.

14. The memory device of claim 2, wherein reading a memory cell selected by a wordline and a bitline of one of the semiconductor layer comprises:

applying a read voltage to the string and ground selection lines of a selected semiconductor layer and unselected wordlines of the selected semiconductor layer;

applying a turn-off voltage to the string and ground selection lines of unselected semiconductor layers;

applying a voltage of 0 volts to a selected wordline of the selected semiconductor layer; and

applying a precharge voltage to a selected bitline.

15. The memory device of claim 1, wherein the semiconductor layers are connected to each other to have equipotentiality with each other.

16. The memory device of claim 1, wherein the semiconductor layers are connected to different upper interconnections such that different well biases are applied to the semiconductor layers.