Memory device and method for programming a nonvolatile memory matrix

• US 20080031051A1
• Filed: 05/21/2007
• Published: 02/07/2008
• Est. Priority Date: 05/19/2006
• Status: Abandoned Application

• Current Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Inventors: Soerensen, Arno
• Application Number:
  US11/802,237
• Publication Number:
  US 20080031051A1
• Time in Patent Office: Days
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits

Abstract

A memory device comprising a nonvolatile memory matrix (EEPROM), a driver for programming the memory matrix, which is connected to the memory matrix to drive a programming potential, a volatile signal memory to drive the driver and a changeable voltage source, which is connected to the volatile signal memory to adjust an output voltage of the volatile signal memory for programming the nonvolatile memory matrix (EEPROM).

Claims

1. A memory device comprising:

a nonvolatile memory matrix;

a driver for programming the memory matrix, the driver being connected to the memory matrix to drive a programming potential;

a volatile signal memory to drive the driver; and

a changeable voltage source, which is connected to the volatile signal memory to adjust an output voltage of the volatile signal memory for programming the nonvolatile memory matrix.

2. The memory device according to claim 1, wherein the changeable voltage source is operably connected to a number of supply terminals of the signal memory.

3. The memory device according to claim 1, wherein the changeable voltage source is operably connected to a number of supply terminals of the driver.

4. The memory device according to claim 1, wherein the volatile signal memory has a static memory and/or a flip-flop.

5. The memory device according to claim 1, wherein the driver has a push-pull stage.

6. The memory device according to claim 1, wherein a decoder is operably connected between the volatile signal memory and the driver.

7. The memory device according to claim 6, wherein the changeable voltage source is operably connected to a number of supply terminals of the decoder.

8. The memory device according to claim 1, wherein the changeable voltage source is operably connected to a first supply voltage terminal of the volatile signal memory to apply a first, changeable supply potential and to a second supply voltage terminal of the volatile signal memory to apply a second, changeable supply potential.

9. The memory device according to claim 8, wherein the changeable voltage source is designed in such a way that the second, changeable supply potential differs by a fixed differential voltage from the first, changeable supply potential.

10. The memory device according to claim 1, wherein the changeable voltage source is operably connected to a third supply voltage terminal of the volatile signal memory to apply a third, changeable supply potential and to a fourth supply voltage terminal of the volatile signal memory to apply a fourth, changeable supply potential.

11. The memory device according to claim 10, wherein the changeable voltage source is designed in such a way that the fourth, changeable supply potential differs by a fixed differential voltage from the third, changeable supply potential.

12. The memory device according to claim 8, wherein the changeable voltage source applies the first supply potential and the third supply potential at the driver.

13. The memory device according to claim 6, wherein the changeable voltage source applies the first supply potential and the third supply potential at the decoder.

14. The memory device according to claim 1, wherein the changeable voltage source has at least one controllable charge pump, preferably two controllable charge pumps with different pump voltages.

15. The memory device according to claim 1, further comprising a limiter for limiting the current drain from the changeable voltage source.

16. The memory device according to claim 15 wherein the limiter for limiting the current drain has two transistors, which are connected to a pulse-forming circuit for driving, and the pulse-forming circuit is designed in such a way that the two transistors are controllable exclusively for writing the volatile signal memory in the conducting state.

17. The memory device according to claim 1, wherein the volatile signal memory has a number of inputs, which are connected to a pulse-forming circuit similar to a pulse gate to generate a pulse from a bit value.

18. The memory device according to claim 1, wherein the volatile signal memory has a first transistor for setting and a second transistor for resetting a static memory, whereby a first control input of the first transistor is connected to a first input and a second control input of the second transistor to a second input.

19. A method for programming a nonvolatile memory matrix, wherein for programming, a programming potential different from the logic potentials is applied, the method comprising:

reading, for programming a bit value, into a volatile signal memory as an H level or an L level; and

increasing all supply potentials of the signal memory by an offset voltage in such a way that the H level or the L level approaches the desired programming potential.