DRAM power bus control
First Claim
1. A method of controlling power distribution on an integrated circuit chip having dynamic random access memory, said dynamic random access memory comprising at least one array operative to be read from and written to and being periodically refreshed in order to maintain stored values, said method comprising:
- powering a delay lock loop circuit with a first voltage;
powering reads and writes of said array with a second voltage; and
powering reads and writes for a finite period of time during said periodic refreshing of said array with a third voltage, wherein said third voltage is higher than said second voltage.
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Accused Products
Abstract
A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.
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Citations
8 Claims
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1. A method of controlling power distribution on an integrated circuit chip having dynamic random access memory, said dynamic random access memory comprising at least one array operative to be read from and written to and being periodically refreshed in order to maintain stored values, said method comprising:
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powering a delay lock loop circuit with a first voltage;
powering reads and writes of said array with a second voltage; and
powering reads and writes for a finite period of time during said periodic refreshing of said array with a third voltage, wherein said third voltage is higher than said second voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification