POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS

• US 20080031072A1
• Filed: 07/31/2006
• Published: 02/07/2008
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Granted Patent: US 7,580,312 B2
• Time in Patent Office: Days
• US Class Current: 365/227
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A power saving system and method are provided. In use, at least one of a plurality of memory circuits is identified that is not currently being accesses. In response to the identification of the at least one memory circuit, a power saving operation is initiated in association with the at least one memory circuit.

Claims

1. A method, comprising:

identifying at least one of a plurality of memory circuits that is not currently being accessed; and

in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit.

2-18. -18. (canceled)

19. A sub-system, comprising:

a component in communication with a plurality of memory circuits and a system, the component operable to initiate a power saving operation in association with at least one of the plurality of memory circuits that is not accessed by the system.

20. (canceled)

21. A method of managing power in an electronic system including a memory, the memory including a plurality of memory circuits, the method comprising:

identifying at least one of the plurality of memory circuits that is not currently being accessed; and

in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit.

22. The method of claim 21, wherein the power saving operation comprises:

a power down operation.

23. The method of claim 22, wherein the power down operation comprises:

a precharge power down operation.

24. The method of claim 21, wherein at least one of the memory circuits has a clock enable input, the method further comprising:

initiating the power saving operation by utilizing the clock enable input of the at least one memory circuit.

25. The method of claim 24, wherein utilizing the clock enable input comprises:

de-asserting the clock enable input of the at least one memory circuit.

26. The method of claim 24, wherein the identifying comprises:

determining whether a page is being accessed in at least one of the plurality of memory circuits.

27. The method of claim 21, wherein the system further includes a component, and wherein;

at least one of the identifying and the initiating is carried out utilizing the component.

28. The method of claim 27, wherein the component includes an advanced memory buffer (AMB).

29. The method of claim 27, wherein the component includes a circuit that is positioned on a dual in-line memory module (DIMM).

30. The method of claim 27, wherein the component includes a memory controller.

31. The method of claim 27, wherein the component includes a register.

32. The method of claim 21, wherein the memory includes a number (x) of the memory circuits, the method farther comprising:

continuously subjecting a lesser number of the memory circuits to the power saving operation.

33. The method of claim 32, wherein the lesser number comprises x−

1.

34. The method of claim 21, wherein the system further includes an interface circuit coupled to interface the plurality of memory circuits and the system, and wherein:

at least one of the identifying and the initiating is carried out utilizing the interface circuit

35. The method of claim 21, wherein the memory circuits each includes dynamic random access memory (DRAM).

36. The method of claim 35, wherein the DRAM of each of the memory circuits each comprises a monolithic DRAM.

37. The method of claim 36, wherein the memory circuits are stacked,

38. The method of claim 36, wherein the memory circuits and the interface circuit are stacked.

39. An apparatus for use with an electronic system, the apparatus comprising:

a plurality of memory circuits; and

a component in communication with the plurality of memory circuits and the system, the component operable to initiate a power saving operation in association with at least one of the plurality of memory circuits that is not accessed by the system.

40. A method of operating a system, the system including a memory including “

x”

memory circuits, the method comprising;

accessing “

p”

of the memory circuits;

while the “

p”

memory circuits are being accessed, performing a power saving operation on “

q”

others of the memory circuits;

wherein “

p”

+“

q”

<

=“

x”

.

41. The method of claim 40, wherein performing the power saving operation comprises:

de-asserting a clock enable input of the “

q”

memory circuits,