SEMICONDUCTOR MEMORY DEVICE

• US 20080032463A1
• Filed: 10/17/2007
• Published: 02/07/2008
• Est. Priority Date: 06/21/2004
• Status: Abandoned Application

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Application Number:
  US11/873,769
• Publication Number:
  US 20080032463A1
• Time in Patent Office: Days
• US Class Current: 438/138
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/742 the device being a field effect transistor for turn-on or turn-off by field effect H01L29/745, H01L29/749
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01038 Strontium [Sr]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A method of forming a circuit includes providing a substrate; providing an interconnect region positioned on the substrate; bonding a device structure to a surface of the interconnect region; and processing the device structure to form a first stack of layers on the interconnect region and a second stack of layers on the first stack. The width of the first stack is different than the width of the second stack.

Claims

1. A method of forming a circuit, comprising:

providing a substrate;

providing an interconnect region positioned on the substrate;

bonding a device structure to a surface of the interconnect region; and

processing the device structure to form a first stack of layers and a second stack of layers on the first stack, the width of the first stack being different than the width of the second stack.

2. The method of claim 1, wherein the step of processing the device structure includes providing at least one of the first and second stacks with tapered sidewalls.

3. The method of claim 1, wherein each of the first and second stacks includes at least one pn junction, the current flow through the pn junction(s) flowing between the first and second stacks.

4. The method of claim 1, further including providing a control terminal in communication with at least one of the stacks.

5. The method of claim 4, wherein the stack and the control terminal operates as one of a vertically oriented transistor device and a vertically oriented thyristor device.

6. The method of claim 1, wherein the substrate carries horizontally oriented electronic devices and the first and second stacks communicate with the horizontally oriented electronic devices through the interconnect region.

7. The method of claim 1, further including providing first and second dielectric regions around the outer periphery of the first and second stacks, respectively.

8. The method of claim 7, further including providing first and second control terminals around the outer periphery of the first and second dielectric regions, respectively, the conductance of the first and second stacks being adjustable in response to signals provided to corresponding first and second control terminals.

9. The method of claim 1, further including choosing the width of the first stack to obtain a desired resistance thereof.

10. A method of forming a circuit, comprising:

providing a substrate which carries an electronic circuit;

providing an interconnect region in communication with the electronic circuit;

bonding a device structure to the interconnect region; and

processing the device structure to form first and second stacks of layers, wherein one of the first and second stacks operates as a transistor and the other one operates as a negative differential resistance device.

11. The method of claim 10, further including forming the first and second stacks so they have different widths.

12. The method of claim 10, wherein the device structure is processed after the substrate is provided.

13. The method of claim 10, wherein the device structure is processed after it is bonded to the interconnect region.

14. The method of claim 10, further including forming the electronic circuit before processing the device structure.

15. The method of claim 10, wherein the transistor is a vertically oriented transistor and the negative differential resistance device is a vertically oriented negative differential device.

16. A method of forming a circuit, comprising:

providing a substrate;

forming electronic circuitry carried by the substrate, wherein the electronic circuitry includes horizontally oriented semiconductor devices;

forming an interconnect region connected to the electronic circuitry;

bonding a device structure so it is coupled to the interconnect region; and

processing the device structure to form a first stack of layers and a second stack of layers on the first stack, the width of the first stack being different than the width of the second stack.

17. The method of claim 16, further including processing the first and second stacks so they operate as vertically oriented semiconductor devices.

18. The method of claim 16, further including processing the first and second stacks so one operates as a transistor and the other operates as a thyristor.

19. The method of claim 18, wherein the first and second stacks are processed after the device structure is bonded so it is coupled to the interconnect region.

20. The method of claim 18, wherein the first and second stacks are processed after the electronic circuitry is formed.