MEMORY ACCESS CONTROLLER AND METHOD THEREOF
First Claim
Patent Images
1. A memory access control apparatus connected to a memory via a bus, comprising:
- at least one memory access master connected to the bus for issuing a memory access instruction including a HLEN signal that represents the burst length of data to be transmitted on the bus; and
a memory access controller coupled to the at least one memory access master for controlling the access to the memory on the basis of the HLEN signal generated by the memory access master.
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Abstract
A memory access controller that improves SDRAM access performance with the enhanced AHB bus protocol includes at least one memory access master for issuing a memory access instruction including an HLEN signal that represents the burst length of the transmitting data; and a memory access controller for controlling the access to the memory on the basis of the HLEN signal generated by the memory access master.
24 Citations
20 Claims
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1. A memory access control apparatus connected to a memory via a bus, comprising:
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at least one memory access master connected to the bus for issuing a memory access instruction including a HLEN signal that represents the burst length of data to be transmitted on the bus; and a memory access controller coupled to the at least one memory access master for controlling the access to the memory on the basis of the HLEN signal generated by the memory access master. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory access controller, comprising:
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at least one memory access slave for receiving a memory access instruction issued by a corresponding memory access master, generating a memory access request and providing the information of the memory access controller back to the corresponding memory access master, wherein the memory access instruction issued by the corresponding memory access master includes a HLEN signal that represents the burst length of the transmitting data; at least one HLEN signal decoder for decoding the HLEN signal included in the memory access instruction issued by the corresponding memory access master; an arbiter for receiving the memory access request generated by the memory access slave and sorting the received memory access requests to generate sequential access commands; a command buffer for sequentially storing the access commands generated by the arbiter; and a command controller for reading the access command stored in the command buffer and generating a memory access instruction to control the transmission of the data. - View Dependent Claims (8, 9, 10, 11)
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12. A memory access control method for controlling access to a memory, comprising the steps of:
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issuing at least one memory access instruction including a HLEN signal that represents a burst length of data to be transmitted over a bus; and controlling the access to the memory on the basis of the HLEN signal. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A memory access control method comprising:
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receiving a memory access instruction, the memory access instruction includes a HLEN signal that represents a burst length of data being transmitted; generating a memory access request on the basis of the memory access instruction; decoding the HLEN signal; receiving the memory access request and sorting the received memory access requests to generate sequential access commands; sequentially storing the access commands; and reading the access command and generating a memory access instruction to control the transmission of the data. - View Dependent Claims (19, 20)
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Specification