Non-volatile memory storage systems for phased garbage collection
First Claim
1. A non-volatile memory storage system, comprising:
- a memory configured to store a storage system firmware;
a non-volatile memory cell array configured to maintain a buffer; and
a processor in communication with the memory and the non-volatile memory cell array, the processor being configured to execute the storage system firmware stored in the memory, the storage system firmware comprising program instructions for,receiving a write command to write a plurality of data to the non-volatile memory cell array, the write command being allocated a timeout period to complete an execution of the write command,performing a portion of a garbage collection operation within the timeout period, andstoring the plurality of data in the buffer.
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Accused Products
Abstract
A non-volatile memory storage system is provided. The non-volatile memory storage system includes a memory configured to store a storage system firmware and a non-volatile memory cell array configured to maintain a buffer. A processor in communication with the memory and the non-volatile memory cell array also is included in the non-volatile memory storage system. Here, the processor is configured to execute the storage system firmware stored in the memory. The storage system firmware comprises program instructions for receiving a write command to write data to the non-volatile memory cell array. The write command is allocated a timeout period to complete an execution of the write command. The storage system firmware also comprises program instructions for performing a portion of a garbage collection operation within the timeout period and for storing the data in the buffer.
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Citations
28 Claims
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1. A non-volatile memory storage system, comprising:
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a memory configured to store a storage system firmware; a non-volatile memory cell array configured to maintain a buffer; and a processor in communication with the memory and the non-volatile memory cell array, the processor being configured to execute the storage system firmware stored in the memory, the storage system firmware comprising program instructions for, receiving a write command to write a plurality of data to the non-volatile memory cell array, the write command being allocated a timeout period to complete an execution of the write command, performing a portion of a garbage collection operation within the timeout period, and storing the plurality of data in the buffer.
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2. A non-volatile memory storage system, comprising:
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a memory configured to store a storage system firmware; a non-volatile memory cell array configured to maintain a write buffer block, the write buffer block being configured to span a plurality of logical addresses; and a processor in communication with the memory and the non-volatile memory cell array, the processor being configured to execute the storage system firmware stored in the memory, the storage system firmware comprising program instructions for, receiving a write command to write a plurality of data to the non-volatile memory cell array, the write command being allocated a timeout period to complete an execution of the write command, asserting a busy signal, performing a portion of a garbage collection operation for a garbage collection time period, writing the plurality of data to the write buffer block, and releasing the busy signal before the timeout period. - View Dependent Claims (3, 4, 5, 6, 7, 8)
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9. A non-volatile memory storage system, comprising:
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a read-only memory (ROM) configured to store a storage system firmware; a memory cell array configured to maintain a write buffer block, the write buffer block being configured to span a plurality of logical addresses; a non-volatile memory cell array; and a processor in communication with the ROM, the memory cell array, and the non-volatile memory cell array, the processor being configured to execute the storage system firmware stored in the ROM, the storage system firmware comprising program instructions for, receiving a first write command to write a first plurality of data to the non-volatile memory cell array, the first write command being allocated a first timeout period to complete a first execution of the first write command; asserting a first busy signal, copying a first portion of a plurality of valid data from one or more first blocks to a second block for a garbage collection time period, writing the first plurality of data to the write buffer block, releasing the first busy signal before the first timeout period, receiving a second write command to write a second plurality of data to the non-volatile memory cell array, the second write command being received after the receiving the first write command, the second write command being allocated a second timeout period to complete a second execution of the second write command, asserting a second busy signal, copying a second portion of the plurality of valid data from the one or more first blocks to the second block for the garbage collection time period, and releasing the second busy signal before the second timeout period. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A non-volatile memory storage system, comprising:
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a memory configured to store a storage system firmware; a non-volatile memory cell array configured to maintain a write buffer block, the write buffer block being configured to span a plurality of logical addresses; and a processor in communication with the memory and the non-volatile memory cell array, the processor being configured to execute the storage system firmware stored in the memory, the storage system firmware comprising program instructions for, receiving a write command to write a plurality of data to the non-volatile memory cell array, the non-volatile memory cell array being allocated a timeout period to complete an execution of the write command, asserting a busy signal, copying a portion of a plurality of valid data from one or more first blocks to a second block for a garbage collection time period, writing the plurality of data to the write buffer block, and releasing the busy signal before the timeout period. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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Specification