Systems and methods for secure transaction management and electronic rights protection

• US 20080034406A1
• Filed: 08/20/2007
• Published: 02/07/2008
• Est. Priority Date: 02/13/1995
• Status: Active Grant

• Current Assignee: Intertrust Technologies Corporation (Fidelio Acquisition Co LLC)
• Original Assignee: Intertrust Technologies Corporation (Fidelio Acquisition Co LLC)
• Inventors: Van Wie, David, Ginter, Karl, Spahn, Francis, Sibert, W., Shear, Victor
• Granted Patent: US 8,181,021 B2
• Time in Patent Office: Days
• US Class Current: 726/2
• CPC Class Codes: G06F 21/1078 Logging; Metering
• CPC Class Codes: G06F 21/1082 Backup or restore
• CPC Class Codes: G06F 21/109 by using specially-adapted hardware at the client
• CPC Class Codes: G06F 21/16 Program or content traceability, e.g. by watermarking
• CPC Class Codes: G06F 21/42 using separate channels for security data
• CPC Class Codes: G06F 21/51 at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/572 Secure firmware programming, e.g. of basic input output system [BIOS]
• CPC Class Codes: G06F 21/608 Secure printing
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/725 operating on a secure reference time value
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G06F 21/87 by means of encapsulation, e.g. for integrated circuits
• CPC Class Codes: G06F 2221/034 Test or assess a computer or a system
• CPC Class Codes: G06F 2221/2101 Auditing as a secondary aspect
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect
• CPC Class Codes: G06F 2221/2135 Metering
• CPC Class Codes: G06F 2221/2137 : Time limited access, e.g. to a computer or data
• CPC Class Codes: G06F 2221/2141 : Access rights, e.g. capability lists, access control lists, access tables, access matrices
• CPC Class Codes: G06F 2221/2143 : Clearing memory, e.g. to prevent the data from being stolen
• CPC Class Codes: G06F 2221/2147 : Locking files
• CPC Class Codes: G06F 2221/2149 : Restricted operating environment
• CPC Class Codes: G06F 2221/2151 : Time stamp
• CPC Class Codes: G06Q 10/10 : Office automation; Time management
• CPC Class Codes: G06Q 20/02 : involving a neutral party, e.g. certification authority, notary or trusted third party [TTP]
• CPC Class Codes: G06Q 20/06 : Private payment circuits, e.g. involving electronic currency used among participants of a common payment scheme
• CPC Class Codes: G06Q 20/12 : specially adapted for electronic shopping systems
• CPC Class Codes: G06Q 20/1235 : with control of digital rights management [DRM]
• CPC Class Codes: G06Q 20/24 : Credit schemes, i.e. "pay after"
• CPC Class Codes: G06Q 20/382 : insuring higher security of transaction
• CPC Class Codes: G06Q 30/06 : Buying, selling or leasing transactions
• CPC Class Codes: G07F 9/026 : for alarm, monitoring and auditing in vending machines or means for indication, e.g. when empty
• CPC Class Codes: H04L 2463/101 : applying security measures for digital rights management data processing systems or methods, specially adapted for commerce, e.g. marketing, shopping, billing, auctions or e-commerce G06Q30/00
• CPC Class Codes: H04L 2463/102 : applying security measure for e-commerce data processing systems or methods, specially adapted for e-commerce G06Q30/00
• CPC Class Codes: H04L 63/00 : Network architectures or network communication protocols for network security cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00; network architectures or network communication protocols for wireless network security H04W12/00; security arrangements for protecting computers or computer systems against unauthorised activity G06F21/00
• CPC Class Codes: H04L 63/04 : for providing a confidential data exchange among entities communicating through data packet networks
• CPC Class Codes: H04L 63/104 : Grouping of entities
• CPC Class Codes: H04L 63/20 : for managing network security; network security policies in general filtering policies H04L63/0227
• CPC Class Codes: H04N 21/2347 : involving video stream encryption
• CPC Class Codes: H04N 21/2541 : Rights Management protecting software against unauthorised usage in a vending or licensing environment G06F21/10; security in data switching network management H04L41/28; security management or policies for network security H04L63/20; access security in wireless networks H04W12/08
• CPC Class Codes: H04N 21/26613 : for generating or managing keys in general key distribution for secret or secure communication involving central third party, e.g. key distribution center [KDC] or trusted third party [TTP] H04L9/083; network support of key management H04L63/06; key management for network security in communication control or processing H04W12/04
• CPC Class Codes: H04N 21/4405 : involving video stream decryption
• CPC Class Codes: H04N 21/4623 : Processing of entitlement messages, e.g. ECM [Entitlement Control Message] or EMM [Entitlement Management Message] arrangements for conditional access to broadcast information or to broadcast-related services H04H60/14
• CPC Class Codes: H04N 21/4627 : Rights management associated to the content security in data switching network management H04L41/28; security management or policies for network security H04L63/20; access security in wireless networks H04W12/08
• CPC Class Codes: H04N 21/8355 : involving usage data, e.g. number of copies or viewings allowed

Abstract

The present invention provides systems and methods for electronic commerce including secure transaction management and electronic rights protection. Electronic appliances such as computers employed in accordance with the present invention help to ensure that information is accessed and used only in authorized ways, and maintain the integrity, availability, and/or confidentiality of the information. Secure subsystems used with such electronic appliances provide a distributed virtual distribution environment (VDE) that may enforce a secure chain of handling and control, for example, to control and/or meter or otherwise monitor use of electronically stored or disseminated information. Such a virtual distribution environment may be used to protect rights of various participants in electronic commerce and other electronic or electronic-facilitated transactions. Secure distributed and other operating system environments and architectures, employing, for example, secure semiconductor processing arrangements that may establish secure, protected environments at each node. These techniques may be used to support an end-to-end electronic information distribution capability that may be used, for example, utilizing the “electronic highway.”

Claims

1. An integrated circuit comprising:

a first processing unit comprising;

a first microprocessor; and

memory;

a first secure processing unit, communicatively coupled to the first processing unit, the first secure processing unit comprising;

a second microprocessor;

a first bus interface unit, the first bus interface unit being operable to restrict access to at least some components of the first secure processing unit by the first processing unit;

random-access memory;

non-volatile memory; and

a direct memory access controller;

an integrated circuit die to which the first processing unit and the first secure processing unit are attached.

2. The integrated circuit of claim 1, in which the first processing unit comprises a second secure processing unit, the second secure processing unit comprising a second bus interface unit, the second bus interface unit being operable to restrict access to at least some components of the second secure processing unit by the first secure processing unit.

3. The integrated circuit of claim 1, in which the at least some components of the first secure processing unit include secret information stored in the non-volatile memory of the first secure processing unit.

4. The integrated circuit of claim 3, in which the secret information comprises at least one cryptographic key

5. The integrated circuit of claim 1, in which the at least some components of the first secure processing unit include secret information stored in the random-access memory of the first secure processing unit.

6. The integrated circuit of claim 1, in which the first processing unit is a device microcontroller.

7. The integrated circuit of claim 1, in which the first processing unit is a communications microcontroller.

8. The integrated circuit of claim 1, in which the integrated circuit comprises a network communications chip.

9. The integrated circuit of claim 1, in which the first secure processing unit is operable to execute software for controlling usage of content objects according to one or more usage rules associated with the content objects.

10. The integrated circuit of claim 9, in which the software for controlling usage of content objects is stored, at least in part, in the non-volatile memory of the first secure processing unit.

11. The integrated circuit of claim 9, in which at least some of the usage rules associated with the content objects are stored in the non-volatile memory of the first secure processing unit.

12. The integrated circuit of claim 1, in which the first secure processing unit further comprises a clock.

13. The integrated circuit of claim 12, in which the first secure processing unit further comprises a battery, the battery being operable to supply power to the clock.

14. The integrated circuit of claim 1, in which the first secure processing unit further comprises a memory management unit.

15. The integrated circuit of claim 14, in which the memory management unit is operable to prevent a less trusted task executing on the first processing unit or the first secure processing unit from modifying a more trusted task executing on the first secure processing unit.

16. The integrated circuit of claim 14, in which the memory management unit is operable to page information into and out of first secure processing unit.

17. The integrated circuit of claim 16, in which the information paged into and out of the first secure processing unit comprises virtual memory pages.

18. The integrated circuit of claim 1, in which the first secure processing unit is operable to encrypt at least some code or other information before storing it in memory external to the first secure processing unit.

19. The integrated circuit of claim 18, in which the first secure processing unit is operable to decrypt at least some code or other information loaded from memory external to the first secure processing unit.

20. The integrated circuit of claim 1, in which the first secure processing unit is operable to cryptographically seal at least some code or other information before storing it in memory external to the first secure processing unit.

21. The integrated circuit of claim 20, in which the first secure processing unit is operable to verify a cryptographic seal associated with information loaded from memory external to the first secure processing unit.

22. The integrated circuit of claim 1, in which the non-volatile memory comprises read-only memory.

23. The integrated circuit of claim 1, in which the non-volatile memory comprises non-volatile random-access memory.

24. The integrated circuit of claim 1, in which the non-volatile memory comprises electrically erasable programmable read only memory (EEPROM).

25. The integrated circuit of claim 1, in which the non-volatile memory comprises flash memory.

26. The integrated circuit of claim 1, in which the non-volatile memory stores kernel programs used to control the first secure processing unit.

27. The integrated circuit of claim 1, in which the non-volatile memory stores one or more load modules.

28. The integrated circuit of claim 1, in which the first processing unit and the first secure processing unit are operable to run asynchronously with respect to each other.

29. An electronic appliance comprising:

an integrated circuit comprising;

a first processing unit comprising;

a first secure processing unit, communicatively coupled to the first processing unit, the first secure processing unit comprising;

a second microprocessor;

a first bus interface unit, the first bus interface unit being operable to restrict access to at least some components of the first secure processing unit by the first processing unit;

random-access memory;

non-volatile memory; and

a direct memory access controller;

an integrated circuit die to which the first processing unit and the first secure processing unit are attached.

random-access memory;

a user interface;

secondary storage, the secondary storage storing right management software that, when executed by the integrated circuit is operable to cause the electronic appliance to control access to a piece of electronic content by enforcing control information securely associated with the piece of electronic content, the control information specifying one or more permitted uses of the piece of electronic content, wherein the rights management software is resistant to tampering by a user of the electronic appliance with enforcement of the control information.