Inverted-trench grounded-source fet structure using conductive substrates, with highly doped substrates

• US 20080035987A1
• Filed: 08/08/2006
• Published: 02/14/2008
• Est. Priority Date: 08/08/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hebert, Francois
• Granted Patent: US 7,633,120 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric linen layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.

Claims

1. An inverted field-effect-transistor (iT-FET) semiconductor device comprising a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate further comprising:

a vertical current conducting channel between said source and said drain controlled by a vertical sidewall gate disposed on sidewalls of a trench and padded by a gate oxide layer attached to said sidewalls of said trench; and

a source-body short structure extending downwardly from a bottom surface of said trench for electrically shorting a body region in said substrate to a source disposed on under a bottom of said trench.

2. The iT-FET semiconductor device of claim 1 further comprising:

a doped body region disposed in said substrate and surrounding a lower portion of said trench encompassing said source region forming a channel region along sidewalls of said trench.

3. The iT-FET semiconductor device of claim 2 further comprising:

a drift region disposed near said top surface of said substrate surrounding an upper portion of said trench and encompassing said drain; and

a linker regions disposed below said drift region and extending downwardly to said doped channel region for linking said drift region and said doped channel region.

4. The iT-FET semiconductor device of claim 2 wherein:

said body-source short structure further comprising a conductive plug extending downwardly from a bottom portion of said trench to said source region.

5. The iT-FET semiconductor device of claim 2 wherein:

said body-source short structure further comprising a conductive plug extending downwardly from a bottom portion of said trench through said source region to said body region.

6. The iT-FET semiconductor device of claim 2 wherein:

said body-source short structure further comprising a titanium silicide plug extending downwardly from a bottom portion of said trench to said source region.

7. The iT-FET semiconductor device of claim 2 wherein:

said body-source short structure further comprising a cobalt silicide plug extending downwardly from a bottom portion of said trench to said source region.

8. The iT-FET semiconductor device of claim 2 wherein:

said body-source short structure further comprising a tungsten plug extending downwardly from a bottom portion of said trench to said source region.

9. The iT-FET semiconductor device of claim 1 wherein:

said trench further comprising a thick spacer-oxide layer disposed on an upper portion of said sidewalls for insulating said vertical sidewall gate from said drain to further reduce a gate-drain coupling capacitance.

10. The iT-FET semiconductor device of claim 1 further comprising:

a P+ doped region extending from a bottom of said source region to a P+ substrate.

11. The iT-FET semiconductor device of claim 10 wherein:

said drain further comprising a N+ doped region disposed on said top of said substrate.

12. The iT-FET semiconductor device of claim 10 wherein:

said doped channel region comprising a P doped region disposed in said substrate and surrounding a bottom portion of said trench extending to said source.

13. The iT-FET semiconductor device of claim 10 wherein:

said bottom of said substrate further comprising a P+ doped contact-enhancement zone for enhancing an electrical contact between said source-body short to said source region.

14. The iT-FET semiconductor device of claim 1 further comprising:

a termination area comprising a trenched gate runner electrically connecting to said vertical sidewall gate for electrically connecting to a gate metal disposed in said termination area.

15. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising a metal oxide semiconductor field effect transistor (MOSFET) device.

16. The iT-FET semiconductor device of claim 1 wherein:

said source and said drain are fully surrounded by said trenched gate for achieving a self-termination configuration.

17. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising an N-channel metal oxide semiconductor field effect transistor (MOSFET) device and said semiconductor substrate is a P-type substrate.

18. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising an N-channel metal oxide semiconductor field effect transistor (MOSFET) device and said semiconductor substrate is a N-type substrate.

19. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising a P channel field effect transistor (FET) device and said semiconductor substrate is a P-type substrate.

20. The iT-FET semiconductor device of claim 1 wherein:

said iT-FET comprising P channel field effect transistor (FET) device and said semiconductor substrate is a N-type substrate.

21. An inverted field-effect-transistor (iT-FET) semiconductor device comprising a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate further comprising:

a vertical current conducting channel between said source and said drain controlled by a vertical sidewall gate disposed on sidewalls of a trench and padded by a gate oxide layer attached to said sidewalls of said trench; and

an integrated gate shield comprising a conductive plug filling a central space in said trench and extending to said source below a bottom of said trench for electrically shorting a body region in said substrate to said source disposed on said bottom of said substrate.

22. The iT-FET semiconductor device of claim 21 further comprising:

a doped channel region disposed in said substrate and surrounding a bottom portion of said trench extending to said source.

23. The iT-FET semiconductor device of claim 22 further comprising:

a drift region disposed near said top surface of said substrate surrounding an upper portion of said trench and encompassing said drain; and

a linker regions disposed below said drift region and extending downwardly to said doped channel region for linking said drift region and said doped channel region.

24. The iT-FET semiconductor device of claim 21 wherein:

said trench further comprising a thick spacer-oxide layer disposed on an upper portion of said sidewalls for insulating said vertical sidewall gate from said drain to further reduce a gate-drain coupling capacitance.

25. The iT-FET semiconductor device of claim 21 wherein:

said source further comprising a P+ doped region disposed on said bottom of said substrate.

26. The iT-FET semiconductor device of claim 21 wherein:

said drain further comprising a N+ doped region disposed on said top of said substrate.

27. The iT-FET semiconductor device of claim 26 wherein:

said doped channel region comprising a P doped region disposed in said substrate and surrounding a bottom portion of said trench extending to said source.

28. The iT-FET semiconductor device of claim 26 wherein:

said bottom of said substrate further comprising a P+ doped contact-enhancement zone for enhancing an electrical contact between said source-body short to said source region.

29. The iT-FET semiconductor device of claim 21 further comprising:

a termination area comprising a trenched gate runner electrically connecting to said vertical sidewall gate for electrically connecting to a gate metal disposed in said termination area.

30. The iT-FET semiconductor device of claim 21 wherein:

said iT-FET comprising a metal oxide semiconductor field effect transistor (MOSFET) device.

31. An inverted field-effect-transistor (iT-FET) semiconductor device comprising:

a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate further comprising a trenched gate placed on sidewalls of a vertical trench wherein said source and drain are fully surrounded by said trenched gate on all sides whereby said iT-FET device achieving a self-termination.

32. A method for manufacturing an iT-FET semiconductor device comprising:

forming a source on a bottom and a drain on a top surface of a semiconductor and forming a trenched gate as a gate layer attached to trench sidewalls for controlling a vertical channel along said trenched gate in said semiconductor substrate.

33. The method of claim 32 further comprising:

forming said trenched gate to fully surround said source and drain all sides whereby said iT-FET device achieving a self-termination.