Trenched MOSFET device with trenched contacts

• US 20080035988A1
• Filed: 09/10/2006
• Published: 02/14/2008
• Est. Priority Date: 08/08/2006
• Status: Active Grant

• Current Assignee: Force Technology
• Original Assignee: Force Technology
• Inventors: Hshieh, Fwu-Iuan
• Granted Patent: US 7,816,729 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a trenched gate under the gate metal runner at a termination area. At least one of the trench-gate fingers intersects with the trenched gate under the gate metal runner near the termination area having trench intersection regions vulnerable to have a polysilicon void and seam developed therein. At least a gate contact trench opened through an insulation layer covering the semiconductor power device wherein the gate contact trench penetrating from the insulation layer and extending into the gate polysilicon and the gate contact trench is opened in an area away from the trench intersection regions and also away from a center portion of said the trenched gate underneath said gate runner metal where a polysilicon void or a seam is likely formed thus avoid the formation of the vulnerable spots.

Claims

1. A trenched semiconductor power device comprising a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a wider trenched gate underneath gate runner metal wherein:

at least one of said trench-gate fingers intersect with said wider trenched gate underneath a gate runner metal having trench intersection regions vulnerable to have a polysilicon void and seam developed therein; and

at least a gate contact trench opened through an insulation layer covering said semiconductor power device wherein said gate contact trench penetrating from said insulation layer and extending into a trench-filling material in said trenched gate underneath gate runner metal and said gate contact trench is opened in an area away from said trench intersection regions between the trench finger and the wider trench gate and also away from a center portion of said wider trenched gate underneath said gate runner metal likely to forming respectively a polysilicon void or seam.

2. The trenched semiconductor power device of claim 1 wherein:

said trench intersection regions constituting a T-shaped intersection region.

3. The trenched semiconductor power device of claim 1 wherein:

said gate contact trench is filled with a conductive gate contact plug.

4. The trenched semiconductor power device of claim 1 wherein:

said gate contact trench is filled with a tungsten gate contact plug.

5. The trenched semiconductor power device of claim 1 wherein:

said gate contact trench is filled with a tungsten gate contact plug surrounded with a Ti/TiN barrier layer.

6. The MOSFET cell of claim 1 further comprising:

An insulation layer covering a top surface over said MOSFET cell wherein said source body contact trench is opened through said insulation layer; and

a thin resistance-reduction conductive layer disposed on a top surface covering said insulation layer and contacting said contact metal plug whereby said resistance-reduction conductive layer having a greater area than a top surface of said contact metal plug for reducing a source-body resistance.

7. The MOSFET cell of claim 1 further comprising:

An insulation layer covering a top surface over said MOSFET cell wherein said source body contact trench is opened through said insulation layer; and

a thin resistance-reduction conductive layer disposed on a top surface covering said Ti/TiN/insulation layer and contacting said contact metal plug whereby said resistance-reduction conductive layer having a greater area than a top surface of said contact metal plug for reducing a source-body resistance.

8. The MOSFET cell of claims 6 and 7 wherein:

said thin resistance-reduction conductive layer comprising a titanium (Ti) layer.

9. The MOSFET cell of claims 6 and 7 wherein:

said thin resistance-reduction conductive layer comprising a titanium(Ti)/titanium nitride (TiN) layer.

10. The trenched semiconductor power device of claim 1 wherein:

said source and gate contact trench is filled with an Aluminum alloy surrounded with a Ti/TiN barrier layer.

11. The trenched semiconductor power device of claim 1 wherein:

said wider trenched gate underneath gate runner metal is configured as an open stripe extending from and intersecting to said trench-gate fingers as an L-shaped trenched gate underneath gate runner metal with said width of gate contact trench is smaller than half of a width of said wider trench-gate.

12. The trenched semiconductor power device of claim 1 wherein:

said wider trenched gate underneath gate runner metal is configured as an open stripe extending from and intersecting to said trench-gate fingers as an expanded square-shaped trenched gate underneath gate runner metal with said width of gate contact trench is smaller than half of a width of said wider trench-gate.

13. The trenched semiconductor power device of claim 1 wherein:

said wider trenched gate underneath gate runner metal is configured as an open stripe extending from and intersecting to said trench-gate fingers as an expanded rectangular-shaped trenched gate underneath gate runner metal with said width of gate contact trench is smaller than half of a width of said wider trench-gate.

14. The trenched semiconductor power device of claim 1 wherein:

said wider trenched gate underneath gate runner metal is configured as an open stripe extending from and intersecting to said trench-gate fingers as an expanded circular trenched gate underneath gate runner metal with said width of gate contact trench is smaller than half of a diameter of said wider trench-gate.

15. The trenched semiconductor power device of claim 1 wherein:

said trenched gate underneath gate runner metal is configured as a no-open-end trenched gate underneath gate runner metal perpendicularly intersecting to said trench-gate fingers from active area. The width of gate contact trench is smaller than half of a width of said wider trench-gate.

16. The trenched semiconductor power device of claim 1 wherein:

said trenched gate underneath gate runner metal is configured as an open stripe extending from and having a greater width than said trench-gate fingers wherein said open stripe allowing a body-dopant region disposed adjacent to a source region of said semiconductor power device connecting to another body dopant region underneath a gate runner metal whereby said gate runner metal can function as a field plate.

17. The trenched semiconductor power device of claim 1 wherein:

said trenched gate underneath gate runner metal is configured as an open stripe extending from and intersecting to said trench-gate fingers as an L-shaped trenched gate underneath gate runner metal having a greater width than said trench-gate fingers wherein said L-shaped open trenched gate underneath gate runner metal allowing a body region disposed adjacent to a source region of said semiconductor power device connecting to another body dopant region underneath a gate runner metal whereby said gate runner metal can function as a field plate

18. The trenched semiconductor power device of claim 1 wherein:

said gate contact trench penetrating from said insulation layer and extending into a trench-filling material of doped polysilicon in said trenched gate underneath gate runner metal.

19. A method for fabricating a trenched semiconductor power device comprising steps of:

forming a trenched gate as an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a trenched gate underneath gate runner metal near a termination area having a trench intersection region and forming each of said transistor cells surrounded by said trenched gate with a body region;

encompassing a source region therein with a drain region formed on a bottom surface of a substrate, and

forming an overlying insulation layer and opening at least a gate contact trench penetrating through said insulation layer and extending into a trench-filling material in said trenched gate under gate runner metal by opening said gate contact trench in an area away from said trench intersection region and away from a polysilicon-seam region near a center portion of said trenched gate underneath said gate runner metal to prevent a vulnerability to a polysilicon void developed in said trench intersection region and in said polysilicon seam regions in said center of the trench gate underneath gate metal runner.