New Structure for Microelectronics and Microsystem and Manufacturing Process

• US 20080036039A1
• Filed: 09/27/2005
• Published: 02/14/2008
• Est. Priority Date: 09/30/2004
• Status: Abandoned Application

• Current Assignee: Soitec S.A.
• Original Assignee: Trait Technology (Shenzhen) Co., Ltd., Shenzhen
• Inventors: Aspar, Bernard
• Application Number:
  US11/575,181
• Publication Number:
  US 20080036039A1
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: B81C 1/00595 Control etch selectivity
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence

Abstract

The invention relates to a process for making a semiconducting structure composed of a surface layer (2), at least one buried layer (4) and a support, comprising: —a first step to make a first layer (44) made of a first material on a first support, and at least one area (26, 28) in this first layer made of a second material with an etching rate greater than the etching rate of the first material, —a second step for the formation of the surface layer (2), by assembly of the structure on a second support, and thinning of at least one of the two supports.

Claims

1-38. -38. (canceled)

39. Process for making a structure comprising a surface layer, at least one buried layer and a support, this process comprising:

a first step to make a first structure, including the formation of a first layer made of a first material on a first support, and at least one area in said first layer made of a second material with an etching rate different from an etching rate of said first material,

then a second step for the formation of the surface layer, by assembly of said first structure with a second support.

40. Process according to claim 39, also comprising thinning of at least one of said two supports.

41. Process according to claim 39, comprising etching of said first layer to form at least one cavity, followed by deposition of said second material in said at least one cavity.

42. Process according to claim 39, said assemble being made by molecular bonding or by gluing.

43. Process according to claim 39, also including a step to produce at least one opening in the surface layer, opening up in the material of the buried layer with the highest etching rate.

44. Process according to claim 43, also including etching of the material with the highest etching rate, to form at least on cavity in the buried layer.

45. Process according to claim 44, said at least one cavity having a circular or square or rectangular or polygonal or elliptical shape or with at least one right angle in a plane parallel to the plane of the subjacent layers and surface layers.

46. Process according to claim 39, the material with the highest etching rate being made of silicon dioxide or thermal silica or polycrystalline silicon or amorphous silicon or silicon nitride.

47. Process according to claim 39, the material with the lower etching rate being made of Si₃N₄ or doped silicon dioxide of the BPSC or PSG type or SiO₂.

48. Process according to claim 39, said surface layer being made of a semiconductor, for example silicon or geranium or a III-V, II-VI semiconductor or a semiconductor compound for example SiGe.

49. Process according to claim 39, said surface layer being made of a piezoelectric or pyro-electric or magnetic material.

50. Process according to claim 39, also comprising a step for formation of at least a part of an electronic or microelectronic or electromechanical or MEMS component in said surface layer.

51. Process according to claim 39, said second material having an etching rate greater than the etching rate of said first material.

52. Process according to claim 51, the surface layer being made by assembly of said first layer with said second support.

53. Process according to claim 39, said second material having an etching rate lower than the etching rate of said first material.

54. Process according to claim 53, also comprising a step for formation of a second layer made of a third material with a lower etching rate than the etching rate of said first material, on said first layer including said first and second materials.

55. Process according to claim 54, said second and third materials being identical and being deposited during the same step.

56. Process according to claim 53, said surface layer being made by assembly of said second layer with said second support.

57. Process according to claim 39, also comprising a polishing step before formation of said surface layer.

58. Process according to claim 39, a side of the surface of said second support to be assembled with said first layer comprising components that will come into contact with said at least one area in said first layer, both wafers being aligned with each other when assembling said first structure with said second support.

59. Device comprising a blank surface layer, at least one buried layer made of a first material, and a support, said buried layer comprising at least one area made of a second material, with an etching rate different from an etching rate of said first material.

60. Device according to claim 59, at least one area made of a second material having a circular or square or rectangular or polygonal or elliptical shape or at least one right angle in a plane parallel to the plane of the buried layer and surface layer.

61. Device according to claim 59, the material with the lower etching rate being an electrical insulator such as silicon dioxide, or thermal silica or polycrystalline silicon or amorphous silicon or silicon nitride.

62. Device according to claim 59, the material with the highest etching rate being made of Si₃Ni₄ or doped silicon dioxide of the BPSC or PSG type or Si₂O₂.

63. Device according to claim 59, said surface layer being made of a semiconductor, of silicon or germanium, or III-V or II-VI semiconductor or a semiconductor compound of SiGe.

64. Device according to claim 59, said surface layer being made of a piezoelectric, or pyro-electric magnetic material.

65. Device according to claim 59, said second material having an etching rate higher than the etching rate of said first material.

66. Device according to claim 59, said second material having an etching rate lower than the etching rate of said first material.

67. Device according to claim 66, also comprising a second buried layer made of a third material with an etching rate lower than the etching rate of said first material.

68. Device according to claim 67, said second and third materials being identical.

69. Device according to claim 59, a ratio of the highest etching rate to the lowest etching rate being greater than 10.

70. Semiconducting device comprising:

a surface layer

a first buried layer comprising areas made of a first material and at least one cavity with a square or rectangular or polygonal or elliptical shape or with at least one right angle in a plane parallel to the plane of the buried layer and layer surface,

a second buried layer made of a second material

and a support.

71. Device according to claim 70, said surface layer being made of a semiconductor, of silicon or germanium or a III-V or II-IV semiconductor or a semiconductor compound of SiGe.

72. Device according to claim 70, said surface layer being made of a piezoelectric, or pyro-electric or magnetic material.

73. Device according to claim 70, also comprising all or part of an electronic or microelectronic or electromechanical or MEMS component in said surface layer, above said cavity formed in said buried layer.

74. Device comprising a surface layer, at least one buried layer, made of a first material, and a support, said at least one buried layer comprising at least two areas, one made of a second material, another one made of a third material, different from said second material, said second and third materials having etching rates different from the etching rate of said first material, a second buried layer made of a material having an etching rate lower than the etching rate of said first material.

75. Device according to claim 74, said second and third materials having etching rates greater than the etching rate of said first material.

76. Device according to claim 74, said second and third materials having etching rates lower than the etching rate of said first material.