SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER

• US 20080036092A1
• Filed: 10/16/2007
• Published: 02/14/2008
• Est. Priority Date: 01/14/2004
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey, Stamper, Anthony
• Granted Patent: US 7,847,409 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/312 Organic layers, e.g. photoresist H01L21/3105, H01L21/32 take precedence; photoresists per se G03C
• CPC Class Codes: H01L 21/3121 Layers comprising organo-silicon compounds
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/3148 Silicon Carbide layers
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO₂. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO₂, SiCOH, or doped silicate glass.

Claims

1. An interconnect structure comprising:

a lower metal wiring level comprising first metal lines positioned within a lower low-k dielectric;

an upper metal wiring level atop said lower metal wiring level, said upper metal wiring level comprising second metal lines positioned within an upper low-k dielectric;

and a plurality of vias through a portion of said upper low-k dielectric electrically connecting said lower metal wiring level and said upper metal wiring level, where said plurality of vias comprise a set of rigid dielectric sidewall spacers.

2. The interconnect structure of claim 1 wherein said set of rigid dielectric sidewall spacers comprise SiCH, SiC, SiNH, SiN, or SiO₂.

3. The interconnect structure of claim 2 wherein each of said set of rigid dielectric sidewall spacers have a thickness ranging from about 10 nm to about 100 nm.

4. An interconnect structure comprising:

a lower metal wiring level comprising first metal lines positioned within a lower low-k dielectric;

a mechanically rigid dielectric positioned on said lower metal wiring level, said mechanically rigid dielectric comprising a plurality of metal vias; and

an upper metal wiring level atop said mechanically rigid dielectric, said upper metal wiring level comprising second metal lines positioned within an upper low-k dielectric, where said plurality of metal vias electrically connect said lower metal wiring level and said upper metal wiring level.

5. The interconnect structure of claim 4 wherein said mechanically rigid dielectric comprises SiO₂, SiCOH, or doped silicate glass.

6. The interconnect structure of claim 4 wherein said plurality of metal vias has a coefficient of thermal expansion matched to said mechanically rigid dielectric.