Integrated circuit wearout detection

• US 20080036487A1
• Filed: 07/27/2007
• Published: 02/14/2008
• Est. Priority Date: 08/09/2006
• Status: Abandoned Application

• Current Assignee: Arm Limited (SoftBank Group Corp.), University of Michigan
• Original Assignee: Arm Limited (SoftBank Group Corp.), University of Michigan
• Inventors: Bradley, Daryl Wayne, Blome, Jason Andrew, Mahlke, Scott
• Application Number:
  US11/878,882
• Publication Number:
  US 20080036487A1
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/31708 Analysis of signal quality G01R31/31901 takes precedence; measuring frequencies or analysing frequency spectra per se G01R23/00; measuring non-linear distortion per se G01R23/20

Abstract

An integrated circuit is provided with latency detecting circuitry for detecting signal generation latency within one or more functional circuits and in response thereto to generate a wearout response. The wearout response can take a variety of different forms such as reducing the operating frequency, increasing the operating voltage, operating task allocation within a multiprocessor system, manufacturing test binning and other wearout responses.

Claims

1. A method of detecting wearout of an integrated circuit having at least one functional circuit, said method comprising:

detecting signal generation latency of at least one signal within a functional circuit; and

in response to said signal generation latency, triggering a wearout response.

2. A method as claimed in claim 1, wherein said wearout response is triggered in response to an increase in said signal generation latency and before failure due to wearout occurs.

3. A method as claimed in claim 1, wherein

said detecting includes averaging said signal generation latency over time to generate an averaged signal generation latency;

and

said triggering is responsive to said averaged signal generation latency.

4. A method as claimed in claim 3, wherein said averaging comprises generating at least a short term average and a long term average.

5. A method as claims in claim 3, wherein said averaging comprises triple smooth exponential moving averaging.

6. A method as claimed in claim 1, wherein said triggering comprises comparing said signal generation latency for a predetermined set of vectors with a predetermined threshold value.

7. A method as claimed in claim 1, wherein said wearout response comprises reducing an operating frequency of said integrated circuit.

8. A method as claimed in claim 1, wherein said wearout response comprises increasing an operating voltage of said integrated circuit.

9. A method as claimed in claim 1, wherein said wearout response comprises decreasing an operating voltage range of said integrated circuit.

10. A method as claimed in claim 1, wherein said integrated circuit comprises a plurality of processing units, said detecting detects wearout in one of said plurality of processing units and said wearout response comprises redistributing task allocation between said plurality of processing units to reduce use of said one of said plurality of processing units at least in respects of said functional unit in which wearout has been detected.

11. A method as claimed in claim 1, wherein said method is performed as part of manufacturing test operations and said wearout response comprises binning said integrated circuits in dependence upon detected susceptibility to wearout.

12. A method as claimed in claim 1, wherein said wearout response comprises applying self test operations targeted at a function unit in which wearout has been detected as increasing.

13. A method as claimed in claim 1, wherein said detecting is performed by comparing occurrence of a transition of a signal within said functional circuit with occurrence of respective transitions in a plurality of reference signals having respective predetermined reference timings.

14. A method as claimed in claim 13, wherein said plurality of reference signals are generated by a plurality of taps from a delay line.

15. An integrated circuit comprising:

at least one functional circuit;

latency detecting circuitry responsive to at least one signal within a functional circuit to detect signal generation latency; and

wearout response triggering circuitry coupled to latency detecting circuitry and responsive to said signal generation latency to trigger a wearout response.

16. An integrated circuit as claimed in claim 15, wherein said wearout response is triggered in response to an increase in said signal generation latency and before failure due to wearout occurs.

17. An integrated circuit as claimed in claim 15, wherein

said latency detecting circuitry averages said signal generation latency over time to generate an averaged signal generation latency;

and

wearout response triggering circuitry is responsive to said averaged signal generation latency.

18. An integrated circuit as claimed in claim 17, wherein said averaging comprises generating at least a short term average and a long term average.

19. An integrated circuit as claims in claim 17, wherein said averaging comprises triple smooth exponential moving averaging.

20. An integrated circuit as claimed in claim 15, wherein said wearout response triggering circuitry compares said signal generation latency for a predetermined set of vectors with a predetermined threshold value.

21. An integrated circuit as claimed in claim 15, wherein said wearout response comprises reducing an operating frequency of said integrated circuit.

22. An integrated circuit as claimed in claim 15, wherein said wearout response comprises increasing an operating voltage of said integrated circuit.

23. An integrated circuit as claimed in claim 15, wherein said wearout response comprises decreasing an operating voltage range of said integrated circuit.

24. An integrated circuit as claimed in claim 15, comprising a plurality of processing units, wherein said latency detecting circuitry detects wearout in one of said plurality of processing units and said wearout response comprises redistributing task allocation between said plurality of processing units to reduce use of said one of said plurality of processing units at least in respect of said functional unit in which wearout has been detected.

25. An integrated circuit as claimed in claim 15, wherein said latency detecting circuitry operates during manufacturing test operations and said wearout response comprises binning said integrated circuits in dependence upon detected susceptibility to wearout.

26. An integrated circuit as claimed in claim 15, wherein said wearout response comprises applying self test operations targeted at a function unit in which wearout has been detected.

27. An integrated circuit as claimed in claim 15, wherein said latency detecting circuitry includes comparison circuitry responsive to occurrence of a transition of a signal within said functional circuit and occurrence of respective transitions in a plurality of reference signals having respective predetermined reference timings.

28. An integrated circuit as claimed in claim 27, wherein said plurality of reference signals are generated by a plurality of taps from a delay line.

29. An integrated circuit comprising:

at least one functional circuit means;

latency detecting means for detecting signal generation latency in at least one signal within a functional circuit; and

wearout response triggering means coupled to said latency detecting circuitry for trigger a wearout response in response to said signal generation latency.