Display

• US 20080036698A1
• Filed: 08/07/2007
• Published: 02/14/2008
• Est. Priority Date: 08/09/2006
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Fujimori, Masaaki, Shiba, Takeo, Kawasaki, Masahiro, Ando, Masahiko, Imazeki, Shuji, Matsuoka, Hideyuki
• Application Number:
  US11/834,736
• Publication Number:
  US 20080036698A1
• Time in Patent Office: Days
• US Class Current: 345/55
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/04 Structural and physical details of display devices
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing

Abstract

A display arranged with, in a matrix way, signal lines for providing brightness information to each of pixels, and scanning lines for selecting, in a predetermined cycle, pixels to be provided with brightness information; intake of the brightness information to each of the pixels being executed by intake of signal voltage of the signal lines via thin-film transistors in each of said pixels, in selecting the scanning lines connected with each of the pixels; and having pixels of n-lines and m-rows, by which the brightness information taken into each of the pixels is retained by capacity thereof, even after the scanning lines connected with each of the pixels become a non-selection state, wherein each of the pixels of each line is provided with at least one semiconductor layer that is common between each of the pixels, and the semiconductor layer is formed in parallel to said signal lines.

Claims

1. A display which is an active matrix type display comprising a plurality of signal lines, a plurality of scanning lines arranged orthogonally to said plurality of signal lines, a plurality of pixels enclosed by said plurality of signal lines and said plurality of scanning lines, and thin-film transistors arranged at each of said plurality of pixels, and a plurality of pixels arranged in a matrix state,

wherein said thin-film transistors have a substrate, a gate electrode, a gate insulating film, a source electrode and a drain electrode, and a semiconductor layer;

and

said semiconductor layer is arranged over a plurality of pixels, and in parallel to said signal lines and linearly.

3. The display according to claim 1, wherein said source electrode and said drain electrode are arranged in parallel to said scanning lines, and in perpendicular to said semiconductor layer and linearly.

5. The display according to claim 1, wherein said gate insulating film is arranged in parallel to said semiconductor layer and linearly.

6. The display according to claim 1,

wherein said gate electrode is formed onto said substrate;

said gate insulating film is formed onto said gate electrode;

said source electrode and said gate electrode are formed onto said gate insulating film; and

said semiconductor layer is formed between said source electrode and said gate electrode.

7. The display according to claim 1,

wherein said gate electrode is formed onto said substrate;

said gate insulating film is formed onto said gate electrode;

said semiconductor layer is formed onto said gate insulating film; and

said source electrode and said gate electrode are formed onto said semiconductor layer.

8. The display according to claim 1,

wherein said source electrode and said gate electrode are formed onto said substrate;

said semiconductor layer is formed onto said source electrode and said gate electrode;

said gate insulating film is formed onto said semiconductor layer; and

said gate electrode is formed onto said gate insulating film.

11. The display according to claim 1, wherein said substrate of said thin-film transistor is an insulating substrate formed by polyethylene terephthalate.

12. The display according to claim 1,

wherein said substrate of said thin-film transistor is an insulating substrate formed by uniaxially drawn polyethylene terephthalate;

and

said semiconductor layer is formed orthogonally to a drawing direction of said insulating substrate.

13. The display according to claim 1, wherein said semiconductor layer is electrically separated from the source electrode of adjacent pixels.

14. The display according to claim 1, wherein said thin-film transistors are arranged in plural in one pixel.

15. The display according to claim 1, wherein said semiconductor layer is formed by an organic material.

2. A display which is an active matrix type display comprising a plurality of signal lines, a plurality of scanning lines arranged orthogonally to said plurality of signal lines, a plurality of pixels enclosed by said plurality of signal lines and said plurality of scanning lines, and thin-film transistors arranged at each of said plurality of pixels, and a plurality of pixels arranged in a matrix state,

wherein said thin-film transistors have a substrate, a gate electrode, a gate insulating film, a source electrode and a drain electrode, and a semiconductor layer;

and

said semiconductor layer is arranged over a plurality of pixels, and in parallel to said scanning lines and linearly.

4. A display which is an active matrix type display comprising a plurality of signal lines, a plurality of scanning lines arranged crosswise with said plurality of signal lines, a plurality of pixels enclosed by said plurality of signal lines and said plurality of scanning lines, and thin-film transistors arranged at each of said plurality of pixels, and a plurality of pixels arranged in a matrix state,

wherein said thin-film transistors have a substrate, a gate electrode, a gate insulating film, a source electrode and a drain electrode, and a semiconductor layer;

having two partition walls arranged onto each of said source electrode and said drain electrode or said gate insulating film, and arranged in parallel to said signal lines and linearly; and

said semiconductor layer is arranged between said two partition walls, over a plurality of pixels, and in parallel to said signal lines and linearly.

9. The display according to claim 4, wherein said two partition walls are formed by a photosensitive material.

10. The display according to claim 4, wherein said two partition walls are formed by a self-assembled monolayer.