ELECTROPHORETIC DISPLAY PANEL AND METHOD OF FABRICATING THE SAME

• US 20080037106A1
• Filed: 08/09/2007
• Published: 02/14/2008
• Est. Priority Date: 08/14/2006
• Status: Active Grant

• Current Assignee: Hydis Technologies Co Ltd (E Ink Holdings Incorporated)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Keun Kyu
• Granted Patent: US 7,715,089 B2
• Time in Patent Office: Days
• US Class Current: 359/296
• CPC Class Codes: G02F 1/133377 Cells with plural compartments or having plurality of liquid crystal microcells partitioned by walls, e.g. one microcell per pixel
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/167 by electrophoresis
• CPC Class Codes: G02F 1/16766 for active matrices
• CPC Class Codes: G02F 1/1679 Gaskets; Spacers; Sealing of cells; Filling or closing of cells
• CPC Class Codes: G02F 1/1681 having two or more microcells partitioned by walls, e.g. of microcup type

Abstract

An electrophoretic display panel with a fast response speed and its fabrication method are disclosed. The electrophoretic display panel includes a first array substrate including a gate line and a data line extending perpendicularly to each other, a thin film transistor connected to the gate line and the data line, and a pixel electrode electrically connected to the thin film transistor. The electrophoretic display panel also includes a second array substrate coupled the first array substrate and including a common electrode capable of forming an electric field with the pixel electrode, a spacer formed on at least one of the first array substrate or the second array substrate to define a charging region in the pixel region; and an electrophoretic medium in the charging region between the first and second array substrates.

Claims

1. An electrophoretic display panel comprising:

a first array substrate including a gate line extending in one direction, a data line extending in a direction that is perpendicular to the gate line, a thin film transistor connected to the gate line and the data line, and a pixel electrode electrically connected to the thin film transistor;

a second array substrate coupled to the first array substrate and including a common electrode that is capable of forming an electric field with the pixel electrode;

a spacer formed on at least one of the first array substrate or the second array substrate to define a charging region in the pixel region; and

an electrophoretic medium placed in the charging region between the first and second array substrates.

2. The electrophoretic display panel of claim 1, wherein the spacer is shaped like gridlines of a lattice overlapping the gate line and the data line.

3. The electrophoretic display panel of claim 1, wherein the spacer is shaped like a stripe overlapping either the gate line or the data line.

4. The electrophoretic display panel of claim 1, wherein the spacer is wider than at least one of the gate line or the data line.

5. The electrophoretic display panel of claim 4, wherein the spacer overlaps at least one of the data line or the gate line and overlaps a portion of the pixel electrode located next to the data line or the gate line.

6. The electrophoretic display panel of claim 1, wherein the spacer has a thin film transistor shielding portion extending from the spacer to cover the thin film transistor.

7. The electrophoretic display panel of claim 6, wherein the thin film transistor shielding portion is thinner than other potions of the spacer.

8. The electrophoretic display panel of claim 1, wherein the spacer is formed of an organic layer including acrylic resin.

9. The electrophoretic display panel of claim 1, wherein the electrophoretic medium comprises pigment particles in the form of powder.

10. The electrophoretic display panel of claim 9, wherein the pigment particles move in the charging region of a vapor phase atmosphere formed by the spacer.

11. The electrophoretic display panel of claim 1, wherein the pixel electrode comprises an opaque conductive layer formed of molybdenum (Mo), chromium (Cr), copper (Cu), or aluminum (Al).

12. The electrophoretic display panel of claim 1, wherein the second array substrate comprises a color filer formed in the pixel region.

13. The electrophoretic display panel of claim 12, wherein the color filter is formed in a region defined by the spacer that is formed on the common electrode.

14. The electrophoretic display panel of claim 12, wherein the color filter is formed between the second array substrate and the common electrode.

15. The electrophoretic display panel of claim 14, further comprising a planarization film on the color filter.

16. The electrophoretic display panel of claim 15, wherein the planarization film comprises an organic layer.

17. A method of fabricating an electrophoretic display panel, comprising:

forming a first array substrate including a gate line extending in one direction, a data line extending in a direction that is perpendicular to the gate line, a thin film transistor connected to the gate line and the data line, and a pixel electrode electrically connected to the thin film transistor;

forming a second array substrate including a common electrode, wherein the common electrode is capable of forming an electric field with the pixel electrode;

forming a spacer arranged on at least one of the first array substrate or the second array substrate to define a charging region in the pixel region;

forming an electrophoretic medium in the charging region; and

attaching the first and second array substrates to each other with the electrophoretic medium disposed between them.

18. The method of claim 17, wherein forming the spacer comprises shaping the spacer like gridlines of a lattice overlapping the gate line and the data line.

19. The method of claim 17, wherein forming the spacer comprises shaping the spacer like a stripe overlapping the gate line or the data line.

20. The method of claim 17, wherein the spacer overlaps at least one of the data line or the gate line and overlaps a portion of the pixel electrode next to the data line or the gate line.

21. The method of claim 17, wherein forming the spacer comprises forming the spacer of an organic layer including an acrylic resin.

22. The method of claim 17, wherein the pixel electrode comprises an opaque conductive layer formed of molybdenum (Mo), chromium (Cr), copper (Cu), or aluminum (Al).

23. The method of claim 17, wherein the spacer has a thin film transistor shielding portion extending from the spacer to cover the thin film transistor.

24. The method of claim 23, further comprising making the thin film transistor shielding portion thinner than other portions of the spacer by using a partial light exposure method.