MEMORY DEVICE WITH SEPARATE READ AND WRITE GATE VOLTAGE CONTROLS
First Claim
1. A circuit comprising:
- at least one local input/output line;
at least one local from/to global input/output multiplexer in signal communication with the at least one local input/output line;
at least one global input/output line in signal communication with the at least one local from/to global input/output multiplexer; and
a local from/to global input/output controller comprising at least one input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the at least one local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation and a gate signal of a third level in the presence of the input operation.
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Accused Products
Abstract
A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line in signal communication with the local from/to global input/output multiplexer, and a local from/to global input/output controller having an input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation, and a gate signal of a third level in the presence of the input operation.
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Citations
34 Claims
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1. A circuit comprising:
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at least one local input/output line; at least one local from/to global input/output multiplexer in signal communication with the at least one local input/output line; at least one global input/output line in signal communication with the at least one local from/to global input/output multiplexer; and a local from/to global input/output controller comprising at least one input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the at least one local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation and a gate signal of a third level in the presence of the input operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A circuit for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit comprising:
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input means for receiving a signal indicative of a read or write mode; first driver means for providing a gate voltage of a first level to the transistor in the read mode in which a selectable local sense amplifier is disabled or the selectable local sense amplifier is not adopted; second driver means for providing a gate voltage of a second level to the transistor in the read mode in which the selectable local sense amplifier is enabled; and third driver means for providing a gate voltage of a third level to the transistor in the write mode.
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18. A method for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the method comprising:
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receiving a signal indicative of a read mode; providing a gate voltage of a first or second level to the transistor in response to the read mode; receiving a signal indicative of a write mode; and providing a gate voltage of a third level to the transistor in response to the write mode, wherein the first or second level is lower than the third level. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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25. A memory device comprising:
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at least one dynamic random access memory (DRAM) bank; at least one local input/output line in signal communication with the at least one DRAM bank; at least one local from/to global input/output multiplexer in signal communication with the at (east one local input/output line; at least one global input/output line in signal communication with the at least one local from/to global input/output multiplexer; and a local from/to global input/output controller comprising at least one input node and an output node the at least one input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the at least one local from/to global input/output multiplexer for providing a gate voltage of a first or second level in the presence of the output operation, and a gate voltage of a third level in the presence of the input operation. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification