MEMORY DEVICE WITH SEPARATE READ AND WRITE GATE VOLTAGE CONTROLS

• US 20080037333A1
• Filed: 03/01/2007
• Published: 02/14/2008
• Est. Priority Date: 04/17/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Kim, Kyoung Ho, Jang, Seong Jin
• Granted Patent: US 7,619,935 B2
• Time in Patent Office: Days
• US Class Current: 365/189.02
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line in signal communication with the local from/to global input/output multiplexer, and a local from/to global input/output controller having an input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation, and a gate signal of a third level in the presence of the input operation.

Claims

1. A circuit comprising:

at least one local input/output line;

at least one local from/to global input/output multiplexer in signal communication with the at least one local input/output line;

at least one global input/output line in signal communication with the at least one local from/to global input/output multiplexer; and

a local from/to global input/output controller comprising at least one input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the at least one local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation and a gate signal of a third level in the presence of the input operation.

2. A circuit as defined in claim 1 wherein:

the at least one local from/to global input/output multiplexer comprises a NMOS transistor;

the controller comprises a voltage controller;

the first, second and third gate signals comprise first, second and third gate voltages, respectively;

the signal indicative of the input operation comprises a write enable signal;

the gate signal of the First level is a high voltage level responsive to the output operation; and

the gate signal of the third level is a higher or boosted voltage level responsive to the input operation.

3. A circuit as defined in claim 2, the voltage controller further comprising another input node disposed for receiving a signal indicative of a block selection:

Wherein the gate signals are enabled in response to the block selection.

4. A circuit as defined in claim 3, further comprising a control unit for providing a local and global input/output control signal:

the voltage controller further comprising another input node disposed for receiving the local and global input/output control signal from the control unit;

wherein the gate signals are enabled in response to the local and global input/output control signal.

5. A circuit as defined in claim 4, the voltage controller further comprising:

a first NAND gate disposed for receiving the signal indicative of the block selection and the local and global input/output control signal; and

a second NAND gate in signal communication with an output of the first NAND gate and disposed for receiving the signal indicative of the input operation.

wherein an output of the second NAND gate is in signal communication with the gate terminal of a transistor, and the output of the first NAND gate is in signal communication with the gate terminals of two transistors.

6. A circuit as defined in claim 1, the circuit further comprising a local sense amplifier in signal communication with the at least one local input/output line, the voltage controller further comprising another input node disposed for receiving a signal indicative of the local sense amplifier being enabled;

wherein if the local sense amplifier is enabled in the output operation the gate signal of the second level which is a low voltage level is provided so that the at least one local from/to global input/output multiplexer is turned off, if the local sense amplifier is disabled in the output operation, the gate signal of the first level which is a high voltage level is provided, and the gate signal of the third level which is a higher or boosted voltage level is provided in the input operation.

7. A circuit as defined in claim 6, the voltage controller further comprising:

a first NAND gate disposed for receiving a signal indicative of a block selection and a local and global input/output control signal;

a second NAND gate disposed for receiving the signal indicative of the input operation and the signal indicative of the local sense amplifier being enabled; and

a third NAND gate in signal communication with an output of the first NAND gate and an output of the second NAND gate;

wherein an output of the third NAND gate is in signal communication with the gate terminal of a transistor, and the output of the first NAND gate is in signal communication with the gate terminals of two transistors.

8. A circuit as defined in claim 1, further comprising at least one load transistor in signal communication with the at least one global input/output line, wherein an undesired read reverse current may be substantially prevented during the output operation by providing the gate signal of the first or second level to the gate of the at least one local from/to global input/output multiplexer, and the first or second level is lower than the third level.

9. A circuit as defined in claim 8, further comprising at least one current sense amplifier in signal communication with the at least one global input/output line via at least one global from/to data input/output multiplexer, wherein the at least one load transistor is activated during the output operation.

10. A circuit as defined in claim 9, further comprising at least one write driver in signal communication with the at least one global input/output line, wherein a write current may he substantially increased during the input operation by providing the gate signal of the third level to the gate of the at least one local from/to global input/output multiplexer, and the third level is higher than the first or second level.

11. A circuit as defined in claim 1, the local from/to global input/output controller further comprising at least three driver transistors, the first driver transistor disposed for providing the gate signal of the first level, the second driver transistor disposed for providing the gate signal of the second level, and the third driver transistor disposed for providing the gate signal of the third level.

12. A circuit as defined in claim 11, the local from/to global input/output controller further comprising a plurality of logic gates in signal communication with the driver transistors, the plurality of logic gates disposed for receiving signals indicative of a write enable and a block select.

13. A circuit as defined in claim 12 wherein the plurality of logic gates are further disposed for receiving at least one of a signal indicative of a local sense amplifier enable or a local and global input/output selection.

14. A circuit as defined in claim 11 wherein the first level is substantially a high voltage, the second level is substantially grounded, and the third level is substantially a higher or boosted voltage.

15. A circuit as defined in claim 14 wherein the first driver transistor has a threshold voltage drop greater than the third driver transistor.

16. A circuit as defined in claim 1 wherein the at least one local input/output line is disposed in signal communication with a dynamic random access memory (DRAM).

17. A circuit for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit comprising:

input means for receiving a signal indicative of a read or write mode;

first driver means for providing a gate voltage of a first level to the transistor in the read mode in which a selectable local sense amplifier is disabled or the selectable local sense amplifier is not adopted;

second driver means for providing a gate voltage of a second level to the transistor in the read mode in which the selectable local sense amplifier is enabled; and

third driver means for providing a gate voltage of a third level to the transistor in the write mode.

18. A method for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the method comprising:

receiving a signal indicative of a read mode;

providing a gate voltage of a first or second level to the transistor in response to the read mode;

receiving a signal indicative of a write mode; and

providing a gate voltage of a third level to the transistor in response to the write mode, wherein the first or second level is lower than the third level.

19. A method as defined in claim 18, further comprising:

selectably disabling a local sense amplifier in the read mode the first level being a high voltage level and the third level being a higher or boosted voltage level; and

selectably enabling the local sense amplifier in the read mode, the second level being a low voltage level and the third level being the higher or boosted voltage level.

20. A method as defined in claim 18, further comprising:

activating a first gate driver transistor in the read mode in which a selectable local sense amplifier is disabled or the selectable local sense amplifier is not adopted;

activating a second gate driver transistor in the read mode in which the selectable local sense amplifier is enabled; and

activating a third gate driver transistor in the write mode;

wherein the first gate driver transistor provides a voltage of the first level the second gate driver transistor provides a voltage of the second level, and the third gate driver transistor provides a voltage of the third level.

21. A method as defined in claim 20.wherein the third level is greater than the first level, and the first level is greater than the second level.

22. A method as defined in claim 20 wherein the first gate driver transistor is NMOS, and the third gate driver transistor is PMOS, the difference in voltage level between the first and third levels substantially comprising a threshold voltage of the first or NMOS gate driver transistor.

23. A method as defined in claim 20, further comprising:

supplying first and second voltage sources where the second is greater than the first;

applying the first supplied voltage source to the first gate driver transistor; and

applying the second voltage source to the third gate driver transistor;

wherein the difference in voltage level between the first and third levels substantially comprises the difference between the supplied first and second voltage sources.

24. A method as defined in claim 18, further comprising:

selectably activating at least one load transistor in the read mode.

25. A memory device comprising:

at least one dynamic random access memory (DRAM) bank;

at least one local input/output line in signal communication with the at least one DRAM bank;

at least one local from/to global input/output multiplexer in signal communication with the at (east one local input/output line;

at least one global input/output line in signal communication with the at least one local from/to global input/output multiplexer; and

a local from/to global input/output controller comprising at least one input node and an output node the at least one input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the at least one local from/to global input/output multiplexer for providing a gate voltage of a first or second level in the presence of the output operation, and a gate voltage of a third level in the presence of the input operation.

26. A memory device as defined in claim 25, the local from/to global input/output controller further comprising:

input means for receiving the signal indicative of the input or output operation;

first driver means for providing the gate voltage of the first level to the multiplexer in the output operation in which a selectable local sense amplifier is disabled or the selectable local sense amplifier is not adopted;

second driver means for providing the gate voltage of the second level to the multiplexer in the output operation in which the selectable local sense amplifier is enabled; and

third driver means for providing the gate voltage of the third level to the multiplexer in the input operation.

27. A memory device as defined in claim 25, further comprising at least one load transistor in signal communication with the at least one global input/output line, wherein an undesired read reverse current may be substantially prevented during the output operation by providing the gate voltage of the first or second level to the gate of the at least one local from/to global input/output multiplexer, and the first or second level is lower than the third level.

28. A memory device as defined in claim 27, further comprising at least one current sense amplifier in signal communication with the at least one global input/output line via at least one global from/to data input/output multiplexer, wherein the at least one load transistor is activated during the output operation.

29. A memory device as defined in claim 25, further comprising at least one write driver in signal communication with the at feast one global input/output line, wherein a write current may be substantially increased during the input operation by providing the gate voltage of the third level to the gate of the at least one local from/to global input/output multiplexer, and the third level is higher than the first or second level.

30. A memory device as defined in claim 25, the local from/to global input/output controller further comprising at least three driver transistors the first driver transistor disposed for providing the gate voltage of the first level, the second driver transistor disposed for providing the gate voltage of the second level, and the third driver transistor disposed for providing the gate voltage of the third level.

31. A memory device as defined in claim 25, the local from/to global input/output controller further comprising a plurality of logic gates in signal communication with the driver transistors, the plurality of logic gates disposed for receiving signals indicative of a write enable and a block select.

32. A memory device as defined in claim 31 wherein the plurality of logic gates are further disposed for receiving at least one of a signal indicative of a local sense amplifier enable or a local and global input/output selection.

33. A memory device as defined in claim 30 wherein the first level is substantially a high voltage, the second level is substantially grounded, and the third level is substantially a higher or boosted voltage.

34. A memory device as defined in claim 33 wherein the first driver transistor has a threshold voltage drop greater than the third driver transistor.