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Interface circuit system and method for performing power saving operations during a command-related latency

  • US 20080037353A1
  • Filed: 10/20/2006
  • Published: 02/14/2008
  • Est. Priority Date: 07/31/2006
  • Status: Active Grant
First Claim
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1. A memory apparatus for use with a system, the memory apparatus comprising:

  • a plurality of memory circuits;

    an interface circuit coupled to communicate with the memory circuits, and for communicating with the system, the interface circuit operable to perform a power management operation on at least a portion of the memory circuits during a latency associated with a command directed to at least a portion of the memory circuits.

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