Apparatus and method for separating a circuit pattern into multiple circuit patterns
First Claim
1. A method for separating an original circuit pattern to be printed on a wafer, into multiple circuit patterns, comprising the steps of:
- obtaining a circuit pattern data;
performing a simulation to obtain image quality information on edges of polygons in the circuit pattern based on the circuit pattern data;
identifying properly printed edges and not-properly printed edges on the wafer according to the image quality information; and
separating the original circuit pattern into multiple circuit patterns such that each of the multiple patterns does not have any not-properly printed edges.
2 Assignments
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Accused Products
Abstract
A method for separating an original circuit pattern to be printed on a wafer, into multiple circuit patterns is disclosed. Simulation to obtain an image log-slope (ILS), normalized image log-slope (NILS), or any other characteristic of an image quality on edges of polygons in the circuit pattern obtained from circuit pattern data is performed. Properly printed edges and not-properly printed edges are identified according to a criterion of an ILS level. The original circuit pattern is separated into multiple circuit patterns such that each of the multiple patterns does not have any not-properly printed edges.
24 Citations
22 Claims
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1. A method for separating an original circuit pattern to be printed on a wafer, into multiple circuit patterns, comprising the steps of:
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obtaining a circuit pattern data;
performing a simulation to obtain image quality information on edges of polygons in the circuit pattern based on the circuit pattern data;
identifying properly printed edges and not-properly printed edges on the wafer according to the image quality information; and
separating the original circuit pattern into multiple circuit patterns such that each of the multiple patterns does not have any not-properly printed edges. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus for separating an original circuit pattern to be printed on a wafer, into multiple circuit patterns, comprising:
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a first unit configured for performing simulation to obtain image quality information on edges of polygons in the circuit pattern obtained from circuit pattern data;
a second unit configured for identifying properly printed edges and not-properly printed edges on the wafer according to the image quality information; and
a third unit configured for separating the original circuit pattern into multiple circuit patterns such that each of the multiple patterns does not have any not-properly printed edges. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A computer readable storage medium storing a computer program for separating an original circuit pattern to be printed on a wafer, into multiple circuit patterns, when executed, causing a computer to perform the steps of:
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obtaining a circuit pattern data;
performing simulation to obtain image quality information on edges of polygons in the circuit pattern based on the circuit pattern data;
identifying properly printed edges and not-properly printed edges on the wafer according to the image quality information; and
separating the original circuit pattern into multiple circuit patterns such that each of the multiple patterns does not have any not-properly printed edges. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A device manufacturing method comprising the steps of:
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(a) providing a substrate that is at least partially covered by a layer of radiation-sensitive material;
(b) providing a projection beam of radiation using an imaging system;
(c) using patterns on masks to endow the projection beam with patterns in its cross-section;
(d) projecting the patterned beam of radiation onto a target portion of the layer of radiation-sensitive material, wherein in step (c), providing a pattern on a mask includes the steps of;
performing simulation to obtain image quality information on edges of polygons in a circuit pattern obtained from circuit pattern data;
identifying properly printed edges and not-properly printed edges on a wafer according to the image quality information; and
separating the original circuit pattern into multiple circuit patterns to be assigned to the masks, respectively, such that each of the multiple patterns does not have any not-properly printed edges.
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Specification