Method of Producing a Plate-Shaped Structure, in Particular, From Silicon, Use of Said Method and Plate-Shaped Structure Thus Produced, in Particular From Silicon

• US 20080038564A1
• Filed: 09/23/2004
• Published: 02/14/2008
• Est. Priority Date: 09/30/2003
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Bruel, Michel
• Granted Patent: US 8,062,564 B2
• Time in Patent Office: Days
• US Class Current: 428/446
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: C30B 33/02 Heat treatment C30B33/04, C30B33/06 take precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

Method for fabricating a structure in the form of a plate, and structure in the form of a plate, in particular formed from silicon, including at least one substrate, a superstrate and at least one intermediate layer interposed between the substrate and the superstrate, in which the intermediate layer comprises at least one base material having distributed therein atoms or molecules termed extrinsic atoms or molecules which differ from the atoms or molecules of the base material, and in which a heat treatment is applied to said plate so that, in the temperature range of said heat treatment, the intermediate layer is plastically deformable and the presence of the selected extrinsic atoms or molecules in the selected base material causes the irreversible formation of micro-bubbles or micro-cavities in the intermediate layer.

Claims

1. A method for fabricating a structure in the form of a plate comprising at least one substrate, a superstrate and at least one intermediate layer interposed between the substrate and the superstrate, the method comprising selecting an intermediate layer comprising at least one base material having distributed therein atoms or molecules termed extrinsic atoms or molecules which differ from the atoms or molecules of the base material, and applying a heat treatment to said structure so that, in the temperature range of said heat treatment, the intermediate layer is plastically deformable and the presence of the selected extrinsic atoms or molecules in the selected base material causes the irreversible formation of micro-bubbles or micro-cavities in the intermediate layer.

2. The method as claimed in claim 1, wherein the heat treatment produces micro-bubbles or micro-cavities which weaken said intermediate layer.

3. The method as claimed in claim 1, wherein the heat treatment produces a rupture of said intermediate layer and, as a result, separation of the substrate and the superstrate.

4. The method of claim 1, further comprising applying forces between the substrate and the superstrate to bring about the rupture of the intermediate layer between the substrate and the superstrate due to the presence of said micro-bubbles or micro-cavities.

5. in the method of claim 1, further comprising chemically attacking the intermediate layer of the structure to at least partially remove said intermediate layer between the substrate and the superstrate.

6. The method of claim 1, wherein the substrate and the superstrate are formed from monocrystalline silicon and the intermediate layer is formed from doped silica.

29. The method as claimed in claim 1, further comprising producing projecting portions in the substrate and/or the superstrate on said intermediate layer side.

30. The method as claimed in claim 29, wherein the projecting portions are rectilinear and extend to the sides of the intermediate layer.

31. The method as claimed in claim 1, wherein at least some of said micro-bubbles or micro-cavities are open-celled and at least some thereof constitute channels.

32. The method as claimed in claim 1, further comprising reducing the thickness of said superstrate and/or substrate.

33. The application of the method as claimed in claim 1 to the fabrication of silicon on insulator (S.O.I.) plates for the fabrication of integrated electronic circuits and/or integrated opto-electronic circuits.

7. A method for fabricating silicon wafers, comprising:

producing a structure in the form of a plate comprising a substrate formed from silicon, a superstrate formed from silicon and a dielectric intermediate layer comprising at least one base material having distributed therein atoms or molecules termed extrinsic atoms or molecules which differ from the atoms or molecules of the base material;

then applying a heat treatment to said structure so that, in the temperature range of the heat treatment, the intermediate layer is plastically deformable and so that the presence of the selected extrinsic atoms or molecules in the selected base material causes the irreversible formation of micro-bubbles or micro-cavities in the intermediate layer.

8. The method as claimed in claim 7, wherein the base material is formed from silica and the extrinsic atoms are atoms of phosphorus or boron, thus forming an intermediate layer of phospho-silicate glass (P.S.G.) or boro-phospho-silicate glass (B.P.S.G.).

9. The method as claimed in claim 8, wherein the concentration of phosphorus is in the range from 6% to 14%.

10. The method as claimed in claim 8, wherein the concentration of boron is in the range from 0% to 4%.

11. The method as claimed in claim 7, wherein the heat treatment is carried out at a temperature in the range from 900°

C. to 1200°

C.

12. The method as claimed in claim 7, wherein the method further comprises, prior to said heat treatment, carrying out an operation for depositing said intermediate layer on the substrate, or respectively the superstrate, and attaching the superstrate, or respectively the substrate, to said intermediate layer by molecular wafer bonding.

13. The method as claimed in claim 7, wherein, on the intermediate layer side, the substrate and the superstrate respectively comprise a thermal silicon oxide.

14. The method as claimed in claim 7, further comprising exerting forces on said structure in a manner such that rupture of said intermediate layer is brought about, resulting in separation of the substrate and superstrate due to the presence of said micro-bubbles or micro-cavities to obtain a wafer constituted by the substrate and/or a wafer constituted by the superstrate.

15. The method as claimed in claim 7, further comprising chemically attacking said intermediate layer of said structure to bring about separation of the substrate and superstrate due to the presence of said micro-bubbles or micro-cavities to obtain a wafer constituted by the substrate and/or a wafer constituted by the superstrate.

16. The method as claimed in claim 7, further comprising producing projecting portions in the substrate and/or the superstrate on said intermediate layer side.

17. The method as claimed in claim 16, wherein the projecting portions are rectilinear and extend to the sides of the intermediate layer.

18. The method as claimed in claim 7, wherein at least some of said micro-bubbles or micro-cavities are open-celled and at least some thereof constitute channels.

19. The method as claimed in claim 7, further comprising reducing the thickness of said superstrate and/or substrate.

20. The application of the method as claimed in claim 7 to the fabrication of silicon on insulator (S.O.I.) plates for the fabrication of integrated electronic circuits and/or integrated opto-electronic circuits.

21. A structure in the form of a plate comprising at least one substrate, a superstrate and at least one intermediate layer interposed between the substrate and the superstrate, wherein the intermediate layer comprises at least one base material having distributed therein atoms or molecules termed extrinsic atoms or molecules which differ from the atoms or molecules of the base material so that, under the effect of a heat treatment, the intermediate layer becomes plastically deformable and the presence of the selected extrinsic atoms or molecules in the selected base material causes the irreversible formation of micro-bubbles or micro-cavities in the intermediate layer.

22. The structure as claimed in claim 21, wherein the substrate and the superstrate are formed from monocrystalline silicon and the intermediate layer is formed from doped silica.

23. The structure as claimed in claim 21, wherein the base material is silica and the extrinsic atoms are atoms of phosphorus or boron, thus forming an intermediate layer of phospho-silicate glass (P.S.G.) or boro-phospho-silicate glass (B.P.S.G.).

24. The structure as claimed in claim 23, wherein the concentration of phosphorus is in the range from 8% to 14%.

25. The structure as claimed in claim 23, wherein the concentration of boron is in the range from 0% to 4%.

26. The structure as claimed in claim 21, wherein the substrate and/or the superstrate have portions projecting into said intermediate layer.

27. The structure as claimed in claim 26, wherein the projecting portions are rectilinear and extend to the sides.

28. The structure as claimed in claim 21, wherein at least some of said micro-bubbles or micro-cavities are open-celled and at least some thereof constitute channels.