Method of manufacturing nitride-based semiconductor light-emitting device

• US 20080038857A1
• Filed: 05/23/2007
• Published: 02/14/2008
• Est. Priority Date: 08/11/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Kim, Hyun-soo, Kim, Kyoung-kook, Choi, Kwang-ki, Song, June-o, Yoon, Suk-ho, Baik, Kwang-hyeon
• Granted Patent: US 7,989,244 B2
• Time in Patent Office: Days
• US Class Current: 438/46
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02439 Materials
• CPC Class Codes: H01L 21/02472 Oxides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01S 5/0213 Sapphire, quartz or diamond based substrates
• CPC Class Codes: H01S 5/0217 Removal of the substrate

Abstract

Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having increased efficiency and increased output properties. The method may include forming a sacrificial layer having a wet etching property on a substrate, forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas atmosphere for crystal growth, and facilitating epitaxial growth of a semiconductor layer to be formed on the protective layer, forming a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the protective layer, and removing the substrate from the semiconductor device by wet etching the sacrificial layer.

Claims

1. A method of manufacturing a nitride-based semiconductor light-emitting device, the method comprising:

forming a sacrificial layer having a wet etching property on a substrate;

forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas atmosphere for crystal growth, and facilitating epitaxial growth of a semiconductor layer to be formed on the protective layer;

forming a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the protective layer; and

removing the substrate from the semiconductor device by wet etching the sacrificial layer.

2. The method of claim 1, wherein the sacrificial layer is formed of one material selected from the group consisting of a first oxide including at least one material selected from the group consisting of SiO₂, GeO₂, and SnO, a second oxide including at least one material selected from the group consisting of ZnO, MgO, BeO, CaO, CdO, MnO, NiO, CuO, Cu₂O, AgO, Ag₂O, and WO₃, a third oxide including at least one material selected from the group consisting of Cr₂O₃, CrO₃, Al₂O₃, In₂O₃, B₂O₃, Ga₂O₃, Ti₂O₃, and CoO, and a fourth oxide including at least one material selected from the group consisting of indium tin oxide (ITO), In_xZn_(1-x)O (IZO), Al-doped ZnO (AZO), and ZnMgO.

3. The method of claim 1, wherein the sacrificial layer is formed of one material selected from the group consisting of silicon nitride (SiN), silicon oxynitride (SiON), and ZnS.

4. The method of claim 1, wherein forming the sacrificial layer includes forming the sacrificial layer by vapor deposition including chemical vapor deposition (CVD) or physical vapor deposition (PVD).

5. The method of claim 1, wherein forming the sacrificial layer includes forming the sacrificial layer to a thickness of about 0.01 μ

m-about 20 μ

m.

6. The method of claim 1, wherein the protective layer is formed of one material selected from the group consisting of SiC, GaAs, AlAs, InAs, AlGaAs, Group-III-nitride, and Group-IV-nitride.

7. The method of claim 6, wherein the Group-III-nitride includes at least one material selected from the group consisting of GaN, AlN, InN, TiN, BN, TiN, InGaN, and AlGaN.

8. The method of claim 6, wherein the Group-IV-nitride includes at least one material selected from the group consisting of SiN, CN, and SiCN.

9. The method of claim 1, wherein forming the protective layer includes forming the protective layer by physical vapor deposition (PVD).

10. The method of claim 9, wherein the PVD includes sputtering, molecular beam epitaxy (MBE) or evaporation.

11. The method of claim 1, wherein forming the protective layer includes forming the protective layer to a thickness of about 0.01 μ

m-about 20 μ

m.

12. The method of claim 1, wherein wet etching the sacrificial layer includes using an acid- or alkali-based etchant that may etch the sacrificial layer selectively.

13. The method of claim 12, wherein the acid-based etchant includes hydrofluoric acid, hydrochloric acid, sulfuric acid, nitric acid or phosphoric acid.

14. The method of claim 1, between forming the sacrificial layer and forming the protective layer, further comprising:

annealing the sacrificial layer in a gas atmosphere including at least one material selected from the group consisting of nitrogen, oxygen, and argon or a vacuum atmosphere.

15. The method of claim 14, wherein annealing the sacrificial layer includes maintaining the sacrificial layer at a temperature of about 100°

C.-about 1400°

C. for about 0.1 minutes-about 180 minutes.

16. The method of claim 15, wherein the annealing temperature is achieved by increasing a temperature of a reaction chamber in which the substrate is mounted at a ratio of about 1°

C.-about 100°

C. per second.

17. The method of claim 1, between forming the protective layer and forming the semiconductor device, further comprising:

annealing the protective layer in a gas atmosphere including at least one material selected from the group consisting of nitrogen, oxygen, and argon or a vacuum atmosphere.

18. The method of claim 17, wherein annealing the protective layer includes maintaining the protective layer at a temperature of about 100°

C.-about 1400°

C. for about 0.1 minutes-about 180 minutes.

19. The method of claim 18, wherein the annealing temperature is achieved by increasing a temperature of a reaction chamber in which the substrate is mounted at a ratio of about 1°

C.-about 100°

C. per second.

20. The method of claim 1, wherein forming the semiconductor device includes forming the semiconductor device by metal organic chemical vapor deposition (MOCVD).

21. The method of claim 1, wherein the substrate is a sapphire substrate, an Si substrate, a GaAs substrate or an SiC substrate.