High performance system-on-chip using post passivation process

• US 20080038869A1
• Filed: 10/19/2007
• Published: 02/14/2008
• Est. Priority Date: 12/21/1998
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Application Number:
  US11/874,910
• Publication Number:
  US 20080038869A1
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/647 : Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 257/92 : Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Abstract

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Claims

1. A method of forming an integrated circuit chip, comprising:

providing a silicon substrate, multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor, a metallization structure over said silicon substrate, wherein said metallization structure is connected to said multiple semiconductor devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said dielectric layer, a first passivation opening in said passivation layer exposing a first pad of said metallization structure, and a second passivation opening in said passivation layer exposing a second pad of said metallization structure, wherein said first and second pads are separate from each other, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;

forming a first conductive structure over said first pad, and a second conductive structure over said second pad;

forming a first solder structure over said first conductive structure, and a second solder structure over said second conductive structure, wherein said forming said first and second solder structures comprises a screen printing process;

mounting a discrete electrical component over said passivation layer, wherein a first contact point of said discrete electrical component is on said first solder structure, and a second contact point of said discrete electrical component is on said second solder structure; and

flowing said first and second solder structures, wherein, after said flowing said first and second solder structures, said first contact point is connected to said first pad through said first solder structure, said first conductive structure and said first passivation opening, and said second contact point is connected to said second pad through said second solder structure, said second conductive structure and said second passivation opening.

2. The method of claim 1, wherein said metallization structure comprises electroplated copper.

3. The method of claim 1 further comprising forming a polymer layer over said passivation layer.

4. The method of claim 3, wherein said forming said polymer layer comprises multiple coating and curing processes.

5. The method of claim 1, wherein said mounting said discrete electrical component comprises mounting a capacitor.

6. The method of claim 1, wherein said mounting said discrete electrical component comprises mounting an inductor.

7. The method of claim 1, wherein said mounting said discrete electrical component comprises mounting a resistor.

8. The method of claim 1, wherein said metallization structure comprises aluminum.

9. A method of forming an integrated circuit chip, comprising:

providing a silicon substrate, multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor, a metallization structure over said silicon substrate, wherein said metallization structure is connected to said multiple semiconductor devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said dielectric layer, a first passivation opening in said passivation layer exposing a first pad of said metallization structure, and a second passivation opening in said passivation layer exposing a second pad of said metallization structure, wherein said first and second pads are separate from each other, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;

forming a first conductive structure over said first pad, and a second conductive structure over said second pad;

forming a first solder structure over said first conductive structure, and a second solder structure over said second conductive structure, wherein said forming said first and second solder structures comprises a ball mounting process;

mounting a discrete electrical component over said passivation layer, wherein a first contact point of said discrete electrical component is on said first solder structure, and a second contact point of said discrete electrical component is on said second solder structure; and

flowing said first and second solder structures, wherein, after said flowing said first and second solder structures, said first contact point is connected to said first pad through said first solder structure, said first conductive structure and said first passivation opening, and said second contact point is connected to said second pad through said second solder structure, said second conductive structure and said second passivation opening.

10. The method of claim 9, wherein said metallization structure comprises electroplated copper.

11. The method of claim 9 further comprising forming a polymer layer on said passivation layer.

12. The method of claim 11, wherein said forming said polymer layer comprises multiple coating and curing processes.

13. The method of claim 9, wherein said mounting said discrete electrical component comprises mounting a capacitor.

14. The method of claim 9, wherein said mounting said discrete electrical component comprises mounting an inductor.

15. The method of claim 9, wherein said mounting said discrete electrical component comprises mounting a resistor.

16. The method of claim 9, wherein said metallization structure comprises aluminum.

17. A method of forming an integrated circuit chip, comprising:

providing a silicon substrate, multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor, a metallization structure over said silicon substrate, wherein said metallization structure is connected to said multiple semiconductor devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said dielectric layer, a first passivation opening in said passivation layer exposing a first pad of said metallization structure, and a second passivation opening in said passivation layer exposing a second pad of said metallization structure, wherein said first and second pads are separate from each other, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;

forming a polymer layer over said passivation layer, wherein a first polymer opening in said polymer layer exposes said first pad, and a second polymer opening in said polymer layer exposes said second pad, wherein said polymer layer has a thickness between 2 and 150 microns;

forming a first conductive structure over said first pad, and a second conductive structure over said second pad;

forming a first solder structure over said first conductive structure, and a second solder structure over said second conductive structure, wherein said forming said first and second solder structures comprises a screen printing process;

mounting a discrete electrical component over said polymer layer, wherein a first contact point of said discrete electrical component is on said first solder structure, and a second contact point of said discrete electrical component is on said second solder structure; and

flowing said first and second solder structures, wherein, after said flowing said first and second solder structures, said first contact point is connected to said first pad through said first solder structure, said first conductive structure, said first polymer opening and said first passivation opening, and said second contact point is connected to said second pad through said second solder structure, said second conductive structure , said second polymer opening and said second passivation opening.

18. The method of claim 17, wherein said metallization structure comprises sputtered aluminum.

19. The method of claim 17, wherein said metallization structure comprises electroplated copper.

20. The method of claim 17, wherein said mounting said discrete electrical component comprises mounting a capacitor.

21. The method of claim 17, wherein said mounting said discrete electrical component comprises mounting an inductor.

22. The method of claim 17, wherein said mounting said discrete electrical component comprises mounting a resistor.

23. The method of claim 17, wherein a vertical distance between said discrete electrical component and said passivation layer is greater than a thickness of said passivation layer, greater than a thickness of said first pad and greater than a thickness of said second pad.

24. The method of claim 17, wherein said forming said polymer layer comprises multiple coating and curing processes.

25. The method of claim 17, wherein said forming said polymer layer comprises forming a polyimide layer.