STRESS ENHANCED MOS CIRCUITS AND METHODS FOR THEIR FABRICATION

• US 20080038886A1
• Filed: 08/11/2006
• Published: 02/14/2008
• Est. Priority Date: 08/11/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pei, Gen
• Granted Patent: US 7,439,120 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

A stress enhanced MOS circuit and methods for its fabrication are provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.

Claims

1. A method for fabricating a stress enhanced MOS circuit, the method comprising the steps of:

forming a polycrystalline silicon gate structure overlying a gate insulator;

depositing a stress liner layer overlying the polycrystalline silicon gate structure;

planarizing the stress liner layer to expose a top portion of the polycrystalline silicon gate structure;

etching the polycrystalline silicon gate structure to remove a first portion of the polycrystalline silicon gate structure, leaving a second portion of the polycrystalline silicon gate structure in contact with the gate insulator, and leaving an etched void bounded in part by the stress liner layer;

filling the void with a electrically conductive stressed material; and

planarizing a surface of the electrically conductive stressed material.

2. The method of claim 1 wherein the step of filling the void comprises the step of filling the void with a compressive stressed titanium nitride.

3. The method of claim 2 wherein the step of depositing a stress liner layer comprises the step of depositing a layer of tensile stressed silicon nitride.

4. The method of claim 1 wherein the step of filling the void comprises the step of filling the void with a tensile stressed material.

5. The method of claim 4 wherein the step of depositing a stress liner layer comprises the step of depositing a layer of compressive stressed silicon nitride.

6. A method for fabricating a stress enhanced MOS circuit, the method comprising the steps of:

depositing and etching a dummy gate material to form a dummy gate electrode;

depositing a layer of insulating material overlying the dummy gate electrode;

removing a portion of the layer of insulating material to expose a top portion of the dummy gate electrode;

removing at least a portion of the dummy gate electrode to leave a void; and

filling the void with a stressed material.

7. The method of claim 6 wherein the stress enhanced MOS circuit is formed on a semiconductor substrate, the method further comprising the steps of:

forming side wall spacers on the dummy gate electrode;

implanting conductivity determining impurities into the semiconductor substrate to form source and drain regions self aligned to the dummy gate electrode; and

wherein the step of depositing a layer of insulating material comprises the step of depositing a layer of stressed silicon nitride overlying the side wall spacers and the source and drain regions.

8. The method of claim 7 wherein the step of depositing a layer of stressed silicon nitride comprises the step of depositing a layer of tensile stressed silicon nitride.

9. The method of claim 7 wherein the step of depositing a layer of stressed silicon nitride comprises the step of depositing a layer of compressive stressed silicon nitride.

10. The method of claim 6 wherein the step of depositing and etching a dummy gate material comprises the steps of:

depositing polycrystalline silicon; and

impurity doping the polycrystalline silicon to establish a desired device threshold voltage.

11. The method of claim 10 wherein the step of removing at least a portion of the dummy gate electrode comprises the step of etching the polycrystalline silicon and leaving at least 10 nm of polycrystalline silicon to fix the desired device threshold.

12. The method of claim 11 wherein the step of filling the void comprises the step of filling the void with a stressed material having a thickness of at least 80 nm.

13. The method of claim 6 wherein the step of filling the void comprises the step of filling the void with a compressive stressed material.

14. The method of claim 6 wherein the step of filling the void comprises the step of filling the void with compressive stressed titanium nitride.

15. The method of claim 6 wherein the step of filling the void comprises the step of filling the void with a tensile stressed material.

16. A stress enhanced MOS circuit comprising:

a semiconductor substrate;

a gate insulator overlying the semiconductor substrate;

a gate electrode overlying the gate insulator, the gate electrode having side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon; and

a stress liner layer overlying the side walls.

17. The MOS circuit of claim 16 wherein the second thickness is at least five times the first thickness.

18. The MOS circuit of claim 16 wherein the electrically conductive stressed material comprises titanium nitride.

19. The MOS circuit of claim 18 wherein the stress liner layer comprises silicon nitride.

20. The MOS circuit of claim 16 wherein the electrically conductive stressed material comprises a tensile stressed material.