METHOD FOR IMPROVED TRENCH PROTECTION IN VERTICAL UMOSFET DEVICES

• US 20080038890A1
• Filed: 08/10/2006
• Published: 02/14/2008
• Est. Priority Date: 08/10/2006
• Status: Abandoned Application

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Tucker, Jesse
• Application Number:
  US11/463,709
• Publication Number:
  US 20080038890A1
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a self-aligned protective layer within a UMOSFET device includes forming a trench within an upper surface of a drift layer, the drift layer of a first polarity type, and epitaxially growing a protective layer on a bottom surface of the trench, the protective layer comprising dopant of the second polarity type. The protective layer is disposed beneath a gate insulating layer formed thereupon.

Claims

1. A method of forming a self-aligned protective layer within a UMOSFET device, the method comprising:

forming a trench within an upper surface of a drift layer, the drift layer comprising a first polarity type; and

epitaxially growing a protective layer on a bottom surface of the trench, the protective layer comprising dopant of the second polarity type;

wherein the protective layer is disposed beneath a gate insulating layer formed thereupon.

2. The method of claim 1, further comprising:

epitaxially growing the protective layer over the upper surface of the drift layer, the sidewalls of the trench, and the bottom surface of the trench;

oxidizing the device such that oxide formation on vertical surfaces of the device occurs at an increased rate with respect to horizontal surfaces of the device; and

removing the oxidized surfaces of the device so as to remove the protective layer from the sidewalls of the trench while maintaining at least a portion of the protective layer on the bottom surface of the trench.

3. The method of claim 2, further comprising repeating the oxidizing and oxidation removal until the protective layer is completely removed from the sidewalls of the trench.

5. The method of claim 1, wherein the first polarity type is N-type and the second polarity type is P-type.

6. The method of claim 1, wherein the first polarity type is N-type silicon carbide and the second polarity type is P-type silicon carbide.

7. A method of forming a silicon carbide UMOSFET device, the method comprising:

forming a drift layer over a drain region substrate, the drift layer and drain region comprising a first polarity type with the drain having a higher dopant concentration with respect to the drift layer;

forming a well region in an upper surface of the drift layer, the well region of a second polarity type opposite the first polarity type;

forming a source region of the first polarity type in an upper surface of the well region;

forming a trench within the upper surface of the drift layer;

epitaxially growing a protective layer on a bottom surface of the trench, the protective layer comprising dopant of the second polarity type;

forming a gate insulating layer on sidewalls of the trench and upon a top surface of the protective layer;

forming a gate electrode contact over a portion of the gate insulating layer;

forming a source electrode contact over the well region and the source region; and

forming a drain electrode contact on a bottom surface of the drain region.

4. The method of claim 8, further comprising removing portions of the protective layer over the upper surface of the drift layer prior to forming the gate insulating layer.

8. The method of claim 7, further comprising:

epitaxially growing the protective layer over the upper surface of the drift layer, the sidewalls of the trench, and the bottom surface of the trench;

oxidizing the device such that oxide formation on vertical surfaces of the device occurs at an increased rate with respect to horizontal surfaces of the device; and

removing the oxidized surfaces of the device so as to remove the protective layer from the sidewalls of the trench while maintaining at least a portion of the protective layer on the bottom surface of the trench.

9. The method of claim 8, further comprising removing portions of the protective layer over the upper surface of the drift layer prior to forming the gate insulating layer.

10. The method of claim 7, wherein the first polarity type is N-type and the second polarity type is P-type.

11. The method of claim 7, wherein the first polarity type is N-type silicon carbide and the second polarity type is P-type silicon carbide.