METHODS FOR ETCHING DOPED OXIDES IN THE MANUFACTURE OF MICROFEATURE DEVICES

• US 20080038896A1
• Filed: 10/12/2007
• Published: 02/14/2008
• Est. Priority Date: 09/01/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rana, Niraj
• Granted Patent: US 7,803,686 B2
• Time in Patent Office: Days
• US Class Current: 438/396
• CPC Class Codes: C09K 13/08 containing a fluorine compound
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 Å/minute.

Claims

1-44. -44. (canceled)

45. A method for forming capacitors on a microfeature workpiece, the workpiece including a plurality of conductive plugs, a first nitride layer over the conductive plugs, a dielectric layer over the first nitride layer, and a second nitride layer over the dielectric layer, the method comprising:

patterning and etching the second nitride layer to form a mask over the dielectric layer;

forming a plurality of openings in the dielectric layer, the individual openings exposing at least a portion of an individual conductive plugs, wherein the dielectric layer includes a doped oxide material;

depositing a first conductive layer in at least a portion of the individual openings and in electrical contact with corresponding conductive plugs, wherein the first conductive layer includes TiN;

depositing a second conductive layer over at least a portion of the first conductive layer in the individual openings, wherein the second conductive layer includes polysilicon; and

removing at least substantially all the dielectric layer from the workpiece with an etchant comprising DI;

HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250;

1, and (b) an etch rate through PSG of greater than 9,000 Å

/minute.

46. The method of claim 45 wherein removing at least substantially all the dielectric layer from the workpiece with an etchant comprises removing the dielectric layer with an etchant having a pH below about 2.0.

47. The method of claim 45 wherein removing at least substantially all the dielectric layer from the workpiece includes removing the dielectric layer with an etchant that etches up to and generally not into the nitride, polysilicon, and/or TiN materials on the workpiece.

48. The method of claim 45 wherein etching up to an generally not into the polysilicon and TiN materials includes removing the dielectric layer with an etchant that has an attack rate of less than about 5 Å

/minute for the polysilicon and/or TiN materials.

49. The method of claim 45 wherein removing at least substantially all the dielectric layer from the workpiece with an etchant includes etching the dielectric layer with an etchant having a selectivity of PSG to nitride of greater than about 300:

1.

50. The method of claim 45 wherein removing at least substantially all the dielectric layer from the workpiece with an etchant includes etching the dielectric layer with an etchant having a selectivity of PSG to nitride of greater than about 400:

1.

51. The method of claim 45 wherein removing at least substantially all the dielectric layer from the workpiece with an etchant includes etching the dielectric layer with an etchant having an etch rate of over about 9,500 Å

/minute through the dielectric layer.

52. The method of claim 45 wherein removing at least substantially all the dielectric layer from the workpiece with an etchant includes etching the dielectric layer with an etchant that generally includes no acetic acid.

53. The method of claim 45 wherein removing at least substantially all the dielectric layer from the workpiece with an etchant comprising DI:

HF and an acid includes etching the dielectric layer with an etchant including DI;

HF;

HNO₃, the etchant having a ratio of DI to HF to HNO₃ of approximately 10;

1;

1.0-2.0.

54. The method of claim 45 wherein removing at least substantially all the dielectric layer from the workpiece with an etchant comprising DI:

HF and an acid includes etching the dielectric layer with an etchant including DI;

HF;

HCl, the etchant having a ratio of DI to HF to HCl of approximately 10;

1;

1.0-2.0.

55. The method of claim 45 wherein removing at least substantially all the dielectric layer from the workpiece with an etchant comprising DI:

HF and an acid includes etching the dielectric layer with an etchant including DI;

HF;

H₂SO₄, the etchant having a ratio of DI to HF to H₂SO₄ of approximately 10;

1;

1.0-2.0.

56. The method of claim 45 wherein removing at least substantially all the dielectric layer from the workpiece with an etchant comprising DI:

HF and an acid includes etching the dielectric layer with an etchant including DI;

HF;

H₃PO₄, the etchant having a ratio of DI to HF to H₃PO₄ of approximately 10;

1;

1.0-2.0.