Electron beam etching device and method

• US 20080038928A1
• Filed: 08/14/2006
• Published: 02/14/2008
• Est. Priority Date: 08/14/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Williamson, Mark J., Sandhu, Gurtej S., Rueger, Neal R.
• Granted Patent: US 7,833,427 B2
• Time in Patent Office: Days
• US Class Current: 438/710
• CPC Class Codes: H01L 21/31116 by dry-etching

Abstract

Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a halogen and carbon containing gas source. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.

Claims

1. A method of semiconductor processing, comprising:

introducing a gas to a semiconductor surface within a processing chamber;

exposing the gas and the semiconductor surface to an energetic beam;

at least partially dissociating the gas to form an etching species to react with a first region of the semiconductor surface; and

concurrently depositing a coating on a second region of the semiconductor surface.

2. The method of claim 1, wherein the energetic beam is an electron beam.

3. The method of claim 2, wherein introducing the gas to the semiconductor surface includes introducing the gas to a surface of a silicon wafer.

4. The method of claim 2, wherein at least partially dissociating the gas to form an etching species to react with the first region of the semiconductor surface includes at least partially dissociating the gas to form an etching species to react with a silicon oxide region.

5. The method of claim 2, wherein concurrently depositing the coating on the second region of the semiconductor surface includes concurrently depositing the coating on a silicon region.

6. The method of claim 2, wherein concurrently depositing the coating includes concurrently depositing a carbon containing coating.

7. A method of semiconductor processing, comprising:

introducing a carbon and halogen containing gas to a semiconductor surface within a processing chamber;

exposing the carbon and halogen containing gas and the semiconductor surface to an electron beam;

at least partially dissociating the gas to form an etching species to etch a silicon oxide region of the semiconductor surface; and

concurrently depositing a carbon containing coating on a silicon region of the semiconductor surface.

8. The method of claim 7, further including adding a noble gas to the processing chamber.

9. The method of claim 7, further including adding a scavenger gas to the processing chamber to remove selected species from the processing chamber.

10. The method of claim 9, wherein adding a scavenger gas includes adding O₂ gas.

11. The method of claim 9, wherein adding a scavenger gas includes adding H₂ gas to reduce the amount of halogen in the processing chamber.

12. A method of semiconductor processing, comprising:

introducing a gas to a semiconductor surface within a processing chamber;

exposing the gas and the semiconductor surface to an electron beam;

at least partially dissociating the gas to form an etching species to react with a first region of the semiconductor surface;

concurrently depositing a coating on a second region of the semiconductor surface; and

imaging the surface using the electron beam as a scanning electron microscope.

13. The method of claim 12, wherein at least partially dissociating the gas to form the etching species includes at least partially dissociating the gas to form a halogen containing species.

14. The method of claim 13, wherein at least partially dissociating the gas to form the halogen containing species includes at least partially dissociating the gas to form a fluorine containing species.

15. The method of claim 12, wherein concurrently depositing the coating includes concurrently depositing a carbon containing coating.

16. The method of claim 12, wherein introducing the gas to the semiconductor surface includes introducing a gas with molecules that include both a halogen and carbon.

17. The method of claim 12, wherein introducing the gas to a semiconductor surface includes introducing CHF₃ gas to the semiconductor surface.

18. The method of claim 17, further including introducing a selected amount of H₂ gas to control a ratio of carbon to fluorine in the coating.

19. A method of forming a semiconductor memory device, comprising:

processing a semiconductor surface to form a number of electronic structures including;

forming a number of memory cells on a semiconductor surface;

forming circuitry to couple the number of memory cells together;

wherein processing a semiconductor surface includes;

introducing a gas to the semiconductor surface within a processing chamber;

exposing the gas and the semiconductor surface to an electron beam;

at least partially dissociating the gas to form an etching species to react with a first region of the semiconductor surface; and

concurrently depositing a coating on a second region of the semiconductor surface.

20. The method of claim 19, wherein at least partially dissociating the gas to form an etching species to react with the first region of the semiconductor surface includes at least partially dissociating the gas to form an etching species to react with a silicon oxide region;

and

concurrently depositing the coating on the second region of the semiconductor surface includes concurrently depositing the coating on a silicon region.

21. The method of claim 19, wherein introducing the gas to the semiconductor surface includes introducing a gas with molecules that include both a halogen and carbon.

22. The method of claim 21, wherein introducing the gas to a semiconductor surface includes introducing CHF₃ gas to the semiconductor surface.

23. The method of claim 19, further including concurrently imaging the surface using the electron beam as a scanning electron microscope.

24. A method of forming an electronic system, comprising:

processing a semiconductor surface to form a semiconductor memory having a number of electronic structures including;

forming a number of memory cells on the semiconductor surface;

forming circuitry to couple the number of memory cells together;

wherein processing the semiconductor surface includes;

introducing a gas to the semiconductor surface within a processing chamber;

exposing the gas and the semiconductor surface to an electron beam;

at least partially dissociating the gas to form an etching species to react with a first region of the semiconductor surface;

concurrently depositing a coating on a second region of the semiconductor surface; and

coupling a controller to the semiconductor memory.

25. The method of claim 24, wherein coupling a controller to the semiconductor memory includes coupling a personal computer processor to the semiconductor memory.

26. The method of claim 24, wherein forming the number of memory cells on the semiconductor surface includes forming a number of flash memory cells on the semiconductor surface.

27. The method of claim 24, wherein introducing the gas to the semiconductor surface includes introducing a gas with molecules that include both a halogen and carbon.

28. The method of claim 27, further including introducing a selected amount of scavenger gas to remove halogen species and control a ratio of carbon to halogen in the coating.

29. The method of claim 24, further including concurrently imaging the surface using the electron beam as a scanning electron microscope.

30. A semiconductor processing system, comprising:

a reaction chamber;

an electron beam source to provide an electron beam to a semiconductor surface within the reaction chamber; and

a source of carbon-halogen gas to react with the electron beam to create reactive species.

31. The semiconductor processing system of claim 30, further including a beam rastering system and a secondary electron detector to image the surface.

32. The semiconductor processing system of claim 30, further including a noble gas source coupled to the reaction chamber.

33. The semiconductor processing system of claim 30, further including a scavenger gas source to selectively remove halogen species from the reaction chamber.

34. The semiconductor processing system of claim 33, wherein a scavenger gas source includes H₂ gas.

35. The semiconductor processing system of claim 30, wherein the source of carbon-halogen gas includes a source of CHF₃ gas.