INTERMODULATION DISTORTION DETECTION AND MITIGATION

• US 20080039045A1
• Filed: 03/30/2007
• Published: 02/14/2008
• Est. Priority Date: 08/08/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Filipovic, Daniel F, Komninakis, Christos
• Granted Patent: US 7,876,867 B2
• Time in Patent Office: Days
• US Class Current: 455/295
• CPC Class Codes: H04B 1/109 by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input
• CPC Class Codes: H04B 1/123 using adaptive balancing or compensation means adaptive filter circuits and algorithms H03H
• CPC Class Codes: H04B 1/525 with means for reducing leakage of transmitter signal into the receiver

Abstract

Techniques for detecting and mitigating intermodulation distortion (IMD) are described. A device (e.g., a cellular phone) obtains digital intermodulation distortion and digitally determines intermodulation distortion in an input signal based on the digital intermodulation distortion. The device may correlate the digital intermodulation distortion with the input signal and determine intermodulation distortion in the input signal based on correlation results. The device may adjust the operation of one or more circuit blocks (e.g., a mixer, an LNA, etc.) in a receiver based on the detected intermodulation distortion in the input signal. Alternatively or additionally, the device may condition the digital intermodulation distortion to obtain conditioned intermodulation distortion matching intermodulation distortion in the input signal and may then subtract the conditioned intermodulation distortion from the input signal.

Claims

1. An apparatus comprising:

at least one processor configured to obtain digital intermodulation distortion and to digitally determine intermodulation distortion in an input signal based on the digital intermodulation distortion; and

a memory coupled to the at least one processor.

2. The apparatus of claim 1, wherein the at least one processor is configured to obtain digital second order intermodulation distortion (IM2) and to digitally determine IM2 in the input signal based on the digital IM2.

3. The apparatus of claim 1, wherein the at least one processor is configured to obtain digital third order intermodulation distortion (IM3) and to digitally determine IM3 in the input signal based on the digital IM3.

4. The apparatus of claim 1, wherein the at least one processor is configured to obtain the digital intermodulation distortion based on a version of a transmit signal.

5. The apparatus of claim 1, wherein the at least one processor is configured to obtain the digital intermodulation distortion based on digital inphase (I) and quadrature (Q) signals corresponding to a version of a transmit signal prior to digital-to-analog conversion.

6. The apparatus of claim 1, wherein the at least one processor is configured to obtain the digital intermodulation distortion based on digital inphase (I) and quadrature (Q) signals corresponding to a version of a transmit signal after frequency upconversion and downconversion.

7. The apparatus of claim 1, wherein the at least one processor is configured to obtain the digital intermodulation distortion based on a squared version of a transmit signal obtained by squaring in analog domain.

8. The apparatus of claim 1, wherein the at least one processor is configured to obtain digital second order intermodulation distortion (IM2) based on squared magnitude of digital inphase (I) and quadrature (Q) signals.

9. The apparatus of claim 8, wherein the at least one processor is configured to obtain digital IM2 with at least one of a variable gain, a variable delay, and an adjustable frequency response.

10. The apparatus of claim 8, wherein the at least one processor is configured to obtain digital IM2 by removing direct current (DC) offset.

11. The apparatus of claim 1, wherein the at least one processor is configured to obtain digital second order intermodulation distortion (IM2) and to obtain digital third order intermodulation distortion (IM3) based on the digital IM2.

12. The apparatus of claim 11, wherein the at least one processor is configured to obtain digital IM3 by multiplying the digital IM2 with inphase (I) and quadrature (Q) signals having jammers included therein.

13. The apparatus of claim 12, wherein the at least one processor is configured to generate the I and Q signals having jammers included therein based on the input signal.

14. The apparatus of claim 11, wherein the at least one processor is configured to obtain digital IM3 with at least one of a variable gain, a variable delay, and an adjustable frequency response.

15. The apparatus of claim 1, wherein the at least one processor is configured to correlate the digital intermodulation distortion with the input signal and to determine intermodulation distortion in the input signal based on correlation results.

16. The apparatus of claim 1, wherein the input signal comprises input inphase (I) and quadrature (Q) signals, and wherein the at least one processor is configured to obtain digital second order intermodulation distortion (IM2) and to correlate the digital IM2 with the input I and Q signals to obtain correlated IM2 I and Q powers.

17. The apparatus of claim 16, wherein the at least one processor is configured to determine power of the digital IM2, to determine powers of the input I and Q signals, and to determine correlation results based on the correlated IM2 I and Q powers, the power of the digital IM2, and the powers of the input I and Q signals.

18. The apparatus of claim 1, wherein the input signal comprises input inphase (I) and quadrature (Q) signals, and wherein the at least one processor is configured to obtain digital I and Q components of third order intermodulation distortion (IM3), to correlate the digital IM3 I component with the input I signal to obtain correlated IM3 I power, and to correlate the digital IM3 Q component with the input Q signal to obtain correlated IM3 Q power.

19. The apparatus of claim 18, wherein the at least one processor is configured to determine powers of the digital IM3 I and Q components, to determine powers of the input I and Q signals, and to determine correlation results based on the correlated IM3 I and Q powers, the powers of the digital IM3 I and Q components, and the powers of the input I and Q signals.

20. The apparatus of claim 1, wherein the at least one processor is configured to adjust operation of at least one circuit block in a receiver based on the determined intermodulation distortion in the input signal.

21. The apparatus of claim 20, wherein the at least one processor is configured to adjust the operation of the at least one circuit block in a closed loop to reduce the determined intermodulation distortion.

22. The apparatus of claim 1, wherein the at least one processor is configured to adjust operation of a mixer in a receiver based on determined second order intermodulation distortion (IM2) in the input signal.

23. The apparatus of claim 1, wherein the at least one processor is configured to adjust gain, or linearity, or both gain and linearity of a low noise amplifier (LNA) in a receiver based on determined third order intermodulation distortion (IM3) in the input signal.

24. The apparatus of claim 1, wherein the at least one processor is configured to condition the digital intermodulation distortion to obtain conditioned intermodulation distortion matching intermodulation distortion in the input signal, and to subtract the conditioned intermodulation distortion from the input signal.

25. The apparatus of claim 24, wherein the at least one processor is configured to condition the digital intermodulation distortion with at least one of a variable gain, a variable delay, and an adjustable frequency response.

26. The apparatus of claim 1, wherein the at least one processor is configured to obtain digital second order intermodulation distortion (IM2), to condition the digital IM2 to obtain conditioned IM2 matching IM2 in the input signal, and to subtract the conditioned IM2 from the input signal.

27. The apparatus of claim 1, wherein the at least one processor is configured to obtain digital third order intermodulation distortion (IM3), to condition the digital IM3 to obtain conditioned IM3 matching IM3 in the input signal, and to subtract the conditioned IM3 from the input signal.

28. A method comprising:

obtaining digital intermodulation distortion; and

digitally determining intermodulation distortion in an input signal based on the digital intermodulation distortion.

29. The method of claim 28, wherein the obtaining digital intermodulation distortion comprises

obtaining digital second order intermodulation distortion (IM2), and

obtaining digital third order intermodulation distortion (IM3) based on the digital IM2.

30. The method of claim 28, wherein the digitally determining intermodulation distortion in the input signal comprises

correlating the digital intermodulation distortion with the input signal, and

determining intermodulation distortion in the input signal based on correlation results.

31. The method of claim 28, further comprising:

adjusting operation of at least one circuit block in a receiver based on the determined intermodulation distortion in the input signal.

32. The method of claim 28, further comprising:

conditioning the digital intermodulation distortion to obtain conditioned intermodulation distortion matching intermodulation distortion in the input signal; and

subtracting the conditioned intermodulation distortion from the input signal.

33. An apparatus comprising:

means for obtaining digital intermodulation distortion; and

means for digitally determining intermodulation distortion in an input signal based on the digital intermodulation distortion.

34. The apparatus of claim 33, wherein the means for digitally determining intermodulation distortion in the input signal comprises

means for correlating the digital intermodulation distortion with the input signal, and

means for determining intermodulation distortion in the input signal based on correlation results.

35. The apparatus of claim 33, further comprising:

means for adjusting operation of at least one circuit block in a receiver based on the determined intermodulation distortion in the input signal.

36. The apparatus of claim 33, further comprising:

means for conditioning the digital intermodulation distortion to obtain conditioned intermodulation distortion matching intermodulation distortion in the input signal; and

means for subtracting the conditioned intermodulation distortion from the input signal.

37. A processor readable media for storing instructions operable to:

obtain digital intermodulation distortion; and

digitally determine intermodulation distortion in an input signal based on the digital intermodulation distortion.

38. The processor readable media of claim 37, and further for storing instructions operable to:

correlate the digital intermodulation distortion with the input signal, and

determine intermodulation distortion in the input signal based on correlation results.

39. The processor readable media of claim 37, and further for storing instructions operable to:

condition the digital intermodulation distortion to obtain conditioned intermodulation distortion matching intermodulation distortion in the input signal; and

subtract the conditioned intermodulation distortion from the input signal.