Network interface device with 10 Gb/s full-duplex transfer rate

• US 20080040519A1
• Filed: 05/01/2007
• Published: 02/14/2008
• Est. Priority Date: 05/02/2006
• Status: Abandoned Application

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Starr, Daryl, Sharp, Colin, Philbrick, Clive
• Application Number:
  US11/799,720
• Publication Number:
  US 20080040519A1
• Time in Patent Office: Days
• US Class Current: 710/39
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures

Abstract

A 10 Gb/s network interface device offloads TCP/IP datapath functions. Frames without IP datagrams are processed as with a non-offload NIC. Receive frames are filtered, then transferred to preallocated receive buffers within host memory. Outbound frames are retrieved from host memory, then transmitted. Frames with IP datagrams without TCP segments are transmitted without any protocol offload, but received frames are parsed and checked for protocol errors, including checksum accumulation for UDP segments. Receive frames without datagram errors are passed to the host and error frames are dumped. Frames with Tcp segments are parsed and error-checked. Hardware checking is performed for ownership of the socket state. TCP/IP frames which fail the ownership test are passed to the host system with a parsing summary. TCP/IP frames which pass the ownership test are processed by a finite state machine implemented by the CPU. TCP/IP frames for non-owned sockets are supported with checksum accumulation/insertion.

Claims

1. A device comprising:

a plurality of control blocks, each of the control blocks containing a combination of information representing the state of a process;

a processor that accesses the control blocks to read and update the information; and

a control block manager that allocates the accessing of the control blocks by the processor.

2. The device of claim 1, wherein the processor has a plurality of contexts, with each context representing a group of resources available to the processor when operating within the context, and the control block manager allows, for each of the control blocks, only one of the contexts to access that control block at one time.

3. The device of claim 1, wherein the process includes communication according to the Transmission Control Protocol (TCP).

4. The device of claim 1, wherein each control block contains information corresponding to TCP.

5. The device of claim 1, wherein each control block contains information corresponding to a different TCP connection.

6. The device of claim 1, wherein each control block contains information corresponding to a different TCP Control Block (TCB).

7. The device of claim 1, wherein each control block contains information corresponding to a transport layer of a communication protocol.

8. The device of claim 1, wherein each control block contains information corresponding to a network layer of a communication protocol.

9. The device of claim 1, wherein each control block contains information corresponding to a Media Access Control (MAC) layer of a communication protocol.

10. The device of claim 1, wherein each control block contains information corresponding to an upper layer of a communication protocol, the upper layer being higher than a transport layer.

11. The device of claim 1, wherein each control block contains information corresponding to at least three layers of a communication protocol.

12. The device of claim 1, wherein the device provides a communication interface for a host.

13. The device of claim 1, wherein at least one of the control blocks has been transferred to the device from a host.

14. The device of claim 1, wherein at least one of the control blocks is not established by the device.

15. The device of claim 1, wherein the control block manager manages storage of the control blocks in a memory.

16. A device comprising:

a control block containing a combination of information representing the state of a process;

a plurality of processors that access the control block to read and update the information; and

a control block manager that allocates the accessing of the control block by the processors.

17. The device of claim 16, wherein the process includes communication according to the Transmission Control Protocol (TCP).

18. The device of claim 16, wherein the control block contains information corresponding to TCP.

19. The device of claim 16, wherein the control block contains information corresponding to a TCP connection.

20. The device of claim 16, wherein the control block contains information corresponding to a TCP Control Block (TCB).

21. The device of claim 16, wherein the device provides a communication interface for a host.

22. The device of claim 16, wherein the control block contains information corresponding to a transport layer of a communication protocol.

23. The device of claim 16, wherein the control block contains information corresponding to a network layer of a communication protocol.

24. The device of claim 16, wherein the control block contains information corresponding to a Media Access Control (MAC) layer of a communication protocol.

25. The device of claim 16, wherein the control block contains information corresponding to an upper layer of a communication protocol, the upper layer being higher than a transport layer.

26. The device of claim 16, wherein the control block contains information corresponding to at least three layers of a communication protocol.

27. The device of claim 16, wherein the processors are pipelined.

28. The device of claim 16, wherein the processors share hardware, with each of the processors occupying a different phase at a single time.

29. The device of claim 16, wherein the control block has been transferred to the device from a host.

30. The device of claim 16, wherein the control block manager manages storage of the control block in a memory.

31. The device of claim 16, wherein each of the processors has a plurality of contexts, with each context representing a group of resources available to the processor when operating within the context, and the control block manager allows only one of the contexts to access the control block at one time.

32. A device comprising:

a plurality of control blocks, each of the control blocks containing a combination of information representing the state of a process;

a plurality of processors that access the control blocks to read and update the information; and

a control block manager that allocates the accessing of the control blocks by the processors.

33. The device of claim 32, wherein each of the processors has a plurality of contexts, with each context representing a group of resources available to the processor when operating within the context, and the control block manager allows only one of the contexts to access any one of the control blocks at one time.

34. The device of claim 32, wherein the control block manager manages storage of the control blocks in a memory.

35. The device of claim 32, wherein the process includes communication according to the Transmission Control Protocol (TCP).

36. The device of claim 32, wherein each control block contains information corresponding to TCP.

37. The device of claim 32, wherein each control block contains information corresponding to a different TCP connection.

38. The device of claim 32, wherein each control block contains information corresponding to a different TCP Control Block (TCB).

39. The device of claim 32, wherein the device provides a communication interface for a host.

40. The device of claim 32, wherein each control block contains information corresponding to a transport layer of a communication protocol.

41. The device of claim 32, wherein each control block contains information corresponding to a network layer of a communication protocol.

42. The device of claim 32, wherein each control block contains information corresponding to a Media Access Control (MAC) layer of a communication protocol.

43. The device of claim 32, wherein each control block contains information corresponding to an upper layer of a communication protocol, the upper layer being higher than a transport layer.

44. The device of claim 32, wherein each control block contains information corresponding to at least three layers of a communication protocol.

45. The device of claim 32, wherein each control block is only accessed by one processor at a time.

46. The device of claim 32, wherein each control block contains information corresponding to a different TCP connection, and each control block is only accessed by one processor at a time.

47. The device of claim 32, wherein the processors are pipelined.

48. The device of claim 32, wherein the processors share hardware, with each of the processors occupying a different phase at a time.

49. The device of claim 32, wherein the device provides a communication interface for a host.

50. The device of claim 32, wherein at least one of the control blocks has been transferred to the device from a host.

51. The device of claim 32, wherein the control block manager grants locks to the plurality of processors, each of the locks being defined to allow access to a specific one of the control blocks by only one of the processors at a time, the control block manager maintaining a queue of lock requests that have been made by all of the processors for each lock.

52. The device of claim 32, wherein the plurality of processors each has a plurality of contexts, with each context representing a group of resources available to the processor when operating within the context, and the control block manager grants locks to the plurality of processors, each of the locks being defined to allow access to a specific one of the control blocks by only one of the contexts at a time.

53. The device of claim 52, wherein the control block manager maintains a queue of requests to access each control block that have been made by all of the contexts for each lock.

54. The device of claim 52, wherein the control block manager maintains a queue of lock requests that have been made by all of the contexts for each lock.

55. The device of claim 32, wherein the plurality of processors each has a plurality of contexts, with each context representing a group of resources available to the processor when operating within the context, and the control block manager allows, for each of the control blocks, only one of the contexts to access that control block at one time.

56. The device of claim 55, wherein the control block manager maintains a queue of requests to access each control block that have been made by all of the contexts for each lock.

57. A device comprising:

a plurality of control blocks stored in a memory, each of the control blocks containing a combination of information representing the state of a process;

a plurality of processors that access the control blocks to read and update the information; and

a control block manager that manages storage of the control blocks in the memory and allocates the accessing of the control blocks by the processors.

58. The device of claim 57, wherein the plurality of processors each has a plurality of contexts, with each context representing a group of resources available to the processor when operating within the context, and the control block manager allows, for each of the control blocks, only one of the contexts to access that control block at one time.

59. The device of claim 57, wherein the control block manager allocates the accessing of the control blocks by the processors based at least in part upon the order in which the processors requested to access each of the control blocks.

60. The device of claim 57, wherein the control block manager allocates the accessing of the control blocks by the processors based at least in part upon a predetermined priority of functions provided by the processors.

61. The device of claim 57, wherein the control block manager allocates the accessing of the control blocks by the processors based at least in part upon a predetermined priority of contexts, wherein each context represents a group of resources available to the processors when operating within the context.