PROCESSING APPARATUS AND METHOD OF MODIFYING SYSTEM CONFIGURATION

• US 20080040526A1
• Filed: 08/09/2007
• Published: 02/14/2008
• Est. Priority Date: 08/11/2006
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Higuchi, Junichi, Suzuki, Jun, Iwata, Atsushi, Hidaka, Youichi
• Granted Patent: US 7,877,521 B2
• Time in Patent Office: Days
• US Class Current: 710/302
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

A virtual PCI Express device 1600 indicates the presence of a pseudo I/O device in a PCI Express initial configuration cycle to reserve a resource space for a device anticipated to be installed in the future, and when an I/O device 1400 is inserted into an unoccupied slot 1605, a virtual PCI Express device control logic 1602 notifies a downstream PCI-PCI bridge 1504 via a hot-plugging control line 1601, and the downstream PCI-PCI bridge 1504 generates an interrupt to a CPU 1100 to notify it of insertion of the I/O device 1400 in conformance with the procedure for hot plugging defined by the PCI-SIG Standards, and configuration software 1000 invoked configures the inserted I/O device 1400.

Claims

1. A processing apparatus connected to a bus, comprising:

a slot;

a pseudo-device; and

a communication relay for relaying communication between said bus and said pseudo-device when no device is connected to said slot, and for relaying communication between said bus and said slot when a device is connected to said slot.

2. A processing apparatus according to claim 1, wherein said pseudo-device comprises one or more configuration registers, and a controller for writing and reading on said configuration registers.

3. A processing apparatus according to claim 2, wherein said pseudo-device retains topology information of said pseudo-device itself, and said controller performs write and read operations on said configuration registers based on said topology information.

4. A processing apparatus according to claim 2, wherein said controller generates an interrupt to a CPU when a device is inserted into said slot.

5. A processing apparatus according to claim 2, wherein said controller generates a first interrupt to a CPU when a device is removed from said slot and said slot is an unoccupied slot, and generates a second interrupt to said CPU when a new device is inserted into said unoccupied slot.

6. A processing apparatus according to claim 2, wherein said controller uses information on a resource space allocated to said pseudo-device to partially or fully make a configuration on said device inserted into said slot.

7. A processing apparatus according to claim 6, wherein said controller generates an interrupt to a CPU upon completion of said configuration.

8. A processing apparatus according to claim 7, wherein said configuration made by said controller before generating said interrupt is directed to a device which is not supported by configuration on a device made by configuration software activated by an interrupt to said CPU.

9. A processing apparatus according to claim 4, wherein said interrupt is in compliance with a procedure for hot plugging defined by PCI-SIG Standards.

10. A processing apparatus according to claim 1, wherein standards of said bus are PCI.

11. A processing apparatus according to claim 1, wherein standards of said bus are PCI-X.

12. A processing apparatus according to claim 1, wherein standards of said bus are PCI Express.

13. A processing apparatus according to claim 12, wherein said processing apparatus is connected to or incorporated into a device constituting a PCI Express switch.

14. A processing apparatus according to claim 13, wherein said device to be connected to said slot is any one of an I/O device, a PCI Express switch, and a downstream PCI-PCI bridge.

15. A processing apparatus according to claim 12, wherein said processing apparatus is connected to or incorporated into a device constituting a root complex.

16. A processing apparatus according to claim 15, wherein said device to be connected to said slot is any one of an I/O device and a PCI Express switch.

17. A method of modifying a system configuration, comprising:

a first step of making an initial configuration by configuration software executed by a CPU in a system with a processing apparatus incorporated into said system, said processing apparatus connected to a bus, and comprising a slot, a pseudo-device, and a communication relay for relaying communication between said bus and said pseudo-device when no device is connected to said slot, and for relaying communication between said bus and said slot when a device is connected to said slot; and

a second step of, when a device is inserted into said slot, making a configuration on said inserted device.

18. A method of modifying a system configuration according to claim 17, wherein said pseudo-device comprises one or more configuration registers, and a controller for performing write and read operations on said configuration registers, and during said initial configuration, said configuration software makes a configuration on said pseudo-device by performing write and read on said configuration registers through said controller.

19. A method of modifying a system configuration according to claim 18, wherein said pseudo-device retains topology information of said pseudo-device itself, and said controller performs write and read operations on said configuration registers based on said topology information.

20. A method of modifying a system configuration according to claim 18, wherein said controller generates an interrupt to said CPU when a device is inserted into said slot.

21. A method of modifying a system configuration according to claim 18, wherein said controller generates a first interrupt to a CPU when a device is removed from said slot and said slot is an unoccupied slot, and generates a second interrupt to said CPU when a new device is inserted into said unoccupied slot.

22. A method of modifying a system configuration according to claim 18, wherein, at said second step, said controller uses information on a resource space allocated to said pseudo-device during said initial configuration, to partially or fully make a configuration on said device inserted into said slot.

23. A method of modifying a system configuration according to claim 22, wherein said controller generates an interrupt to said CPU upon completion of said configuration.

24. A method of modifying a system configuration according to claim 23, wherein said configuration made by said controller before generating said interrupt is directed to a device which is not supported by configuration on a device made by configuration software activated by an interrupt to said CPU.

25. A method of modifying a system configuration according to claim 20, wherein said interrupt is in compliance with a procedure for hot plugging defined by PCI-SIG Standards.

26. A method of modifying a system configuration according to claim 25, wherein said configuration made by said configuration software activated by said interrupt is in compliance with said procedure for hot plugging defined by said PCI-SIG Standards.

27. A method of modifying a system configuration according to claim 17, wherein standards of said bus are PCI.

28. A method of modifying a system configuration according to claim 17, wherein standards of said bus are PCI-X.

29. A method of modifying a system configuration according to claim 17, wherein standards of said bus are PCI Express.

30. A method of modifying a system configuration according to claim 29, wherein said processing apparatus is connected to or incorporated into a device constituting a PCI Express switch, and said device to be connected to said slot is any one of an I/O device, a PCI Express switch, and a downstream PCI-PCI bridge.

31. A method of modifying a system configuration according to claim 29, wherein said processing apparatus is connected to or incorporated into a device constituting a root complex, and said device to be connected to said slot is any one of an I/O device and a PCI Express switch.