DIAGNOSING MIXED SCAN CHAIN AND SYSTEM LOGIC DEFECTS

• US 20080040637A1
• Filed: 08/14/2007
• Published: 02/14/2008
• Est. Priority Date: 08/14/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Guo, Ruifeng, Huang, Yu, Cheng, Wu-Tung
• Granted Patent: US 7,788,561 B2
• Time in Patent Office: Days
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318569 Error indication, logging circuits

Abstract

Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.

Claims

1. A method, comprising:

receiving a failure log indicative of failing test bits observed during testing of an electronic circuit, the electronic circuit having at least one defect in system logic and at least one defect in a scan chain;

identifying one or more fault suspects in the system logic of the electronic circuit;

identifying one or more fault suspects in the at least one scan chain of the electronic circuit; and

storing a description of the identified one or more fault suspects in the system logic and of the identified one or more fault suspects in the at least one scan chain in one or more computer-readable media.

2. The method of claim 1, wherein at least one of the one or more fault suspects in the system logic obscures the detectability of at least one of the fault suspects in the at least one scan chain, or wherein at least one of the fault suspects in the at least one scan chain obscures the detectability of at least one of the fault suspects in the system logic.

3. The method of claim 1, wherein the one or more fault suspects in the system logic are identified before the one or more fault suspects in the at least one scan chain are identified.

4. The method of claim 1, wherein the one or more fault suspects in the at least one scan chain are identified before the one or more fault suspects in the system logic are identified.

5. The method of claim 1, further comprising at least one of:

identifying one or more additional fault suspects in the system logic using the identified one or more fault suspects in the at least one scan chain; and

identifying one or more additional fault suspects in the at least one scan chain using the identified one or more fault suspects in the system logic.

6. The method of claim 1, wherein the identifying one or more fault suspects in the at least one scan chain comprises:

masking one or more potential system logic defect signals in a representation of the electronic circuit; and

using a scan chain defect diagnosis technique to identify the one or more fault suspects in the at least one scan chain.

7. The method of claim 6, wherein the masking the one or more potential system logic defect signals in the representation of the electronic circuit comprises:

identifying a set of one or more logic signals associated with the identified one or more fault suspects in the system logic; and

masking one or more logic gates in the electronic circuit corresponding to the identified set of one or more signals.

8. The method of claim 7, wherein the identifying the set of one or more logic signals associated with the identified one or more fault suspects in the system logic comprises identifying logic signals in one or more logic cones associated with one or more failing outputs of the system logic.

9. The method of claim 8, further comprising performing at least one of a union operation or an intersection operation between the identified logic signals of at least two of the logic cones.

10. The method of claim 6, wherein the masking the one or more potential system logic defect signals in the representation of the electronic circuit comprises changing one or more logic gates associated with the one or more potential system logic defects into X-mask gates.

11. The method of claim 1, wherein the identifying one or more fault suspects in the system logic comprises:

receiving a description of failing bits identified as being caused by system logic defects and not by scan chain defects;

receiving modified scan patterns, the modified scan patterns comprising scan patterns used during the testing of the electronic circuit modified to mask loading and unloading values on faulty scan chains; and

performing logic diagnosis using the description of the failing bits and the modified scan patterns.

12. The method of claim 11, further comprising:

modifying the scan patterns used during the testing of the electronic circuit so that the loading values in scan chains comprising the fault suspects in the at least one scan chain are masked;

performing a good machine simulation of the electronic circuit using the modified scan patterns;

modifying good machine simulation results so that the unloading values in the scan chains comprising the fault suspects in the at least one scan chain are masked; and

storing the modified loading and unloading values in one or more computer-readable media.

13. The method of claim 11, wherein the modified scan patterns are compressed scan patterns.

14. The method of claim 1, wherein the circuit design comprises a compactor outputting to one or more channels, and wherein the at least one scan chain is coupled to a faulty channel via the compactor.

15. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 1.

16. One or more computer-readable media storing the description of the identified one or more fault suspects in the system logic and of the identified one or more fault suspects in the at least one scan chain generated by the method of claim 1.

17. An electronic circuit having one or more repaired defects that were diagnosed according to the method of claim 1.

18. A system comprising:

a component configured to receive a failure log indicative of failing test bits observed during testing of an electronic circuit, the electronic circuit comprising system logic and one or more scan chains and having at least one defect in the system logic and at least one defect in the one or more scan chains;

a component configured to identify one or more fault suspects in the system logic of the electronic circuit; and

a component configured to identify one or more fault suspects in the one or more scan chains of the electronic circuit.

19. The system of claim 18, further comprising a component configured to transmit the log indicative of failing test bits observed during the testing of the electronic circuit.

20. One or more computer-readable media comprising instructions configured to cause a computer to perform a method comprising:

performing logic diagnosis on an electronic circuit while masking one or more faulty scan chains in the electronic circuit to produce logic diagnosis results;

performing scan chain diagnosis on the electronic circuit while masking one or more system logic defects in the electronic circuit to produce scan chain diagnosis results; and

storing the logic diagnosis results and the scan chain diagnosis results.

21. The one or more computer-readable media of claim 20, wherein the method further comprises performing further logic diagnosis on the electronic circuit based at least in part on the scan chain diagnosis results.

22. The one or more computer-readable media of claim 20, wherein the method further comprises performing further scan chain diagnosis on the electronic circuit based at least in part on the logic diagnosis results.

23. The one or more computer-readable media of claim 20, wherein the electronic circuit comprises a compactor.

24. A method, comprising:

receiving a failure log indicative of failing test bits observed during testing of an electronic circuit;

performing chain diagnosis for the at least one scan chain to produce chain diagnosis results, the chain diagnosis results comprising one or more scan chain fault suspects;

determining scores for one or more of the scan chain fault suspects, the score for a respective one of the scan chain fault suspects indicating whether the respective scan chain fault suspect completely or partially explains the failing test bits observed; and

storing the scores in one or more computer-readable media.

25. The method of claim 24, wherein the scores are determined on a pattern-by-pattern basis.

26. The method of claim 24, wherein the scores are determined using bit-based scoring.

27. The method of claim 24, further comprising reducing the number of scan chain fault suspects from the scan chain results using the determined scores.

28. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 24.

29. One or more computer-readable media storing the description of the identified one or more fault suspects in the system logic and of the identified one or more fault suspects in the at least one scan chain identified by the method of claim 24.

30. An electronic circuit having one or more repaired defects that were diagnosed according to the method of claim 24.

31. A method for diagnosing system logic faults in an electronic circuit, the method comprising:

receiving test results obtained by applying scan pattern loading values to the electronic circuit during testing, the test results including failing bits caused by one or more system logic defects in the electronic circuit;

receiving modified scan patterns, the modified scan patterns comprising the scan pattern loading values modified such that values loaded into faulty scan chains have an unknown value, the modified scan patterns further comprising scan pattern unloading values modified such that values unloaded from the faulty scan chains have the unknown value; and

performing system logic diagnosis of the electronic circuit using the failing bits caused by the one or more system logic values and the modified scan patterns.

32. The method of claim 31, wherein the scan pattern unloading values are obtained by performing a good machine simulation using the modified loading values.

33. The method of claim 31, further comprising performing chain diagnosis of the electronic circuit using results from the system logic diagnosis.

34. The method of claim 31, further comprising:

receiving a failure log indicative of failing test bits observed during testing of the electronic circuit with the unmodified scan pattern loading values; and

evaluating the failing test bits in the failure log to identify the failing bits caused by the one or more system logic defects in the circuit.

35. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 31.

36. One or more computer-readable media storing the description of the identified one or more fault suspects in the system logic and of the identified one or more fault suspects in the at least one scan chain identified by the method of claim 31.

37. An electronic circuit having one or more repaired defects that were diagnosed according to the method of claim 31.

38. A method of analyzing data from a test of an electronic circuit having one or more system logic defects and one or more scan chain defects, the data indicating the presence of the one or more system logic defects and the one or more scan chain defects, the method comprising:

identifying from the data a group of one or more failing bits determined as being caused by the one or more system logic defects; and

storing the identified group of one or more failing bits in one or more computer-readable media.

39. The method of claim 38, wherein the identifying from the data group of one or more failing bits determined as being caused by the one or more system logic defects comprises:

identifying a faulty scan chain or a faulty output channel in the electronic circuit;

modifying a representation of the electronic circuit such that scan cells in the identified faulty scan chain or coupled to the identified faulty output channel always output an unknown value;

simulating one or more scan patterns using the modified representation to produce simulation results; and

based on the simulation results, identifying the group of the one or more failing bits determined as being caused by the one or more system logic defects.

40. The method of claim 39, wherein the identifying the group of the one or more failing bits determined as being caused by the one or more system logic defects comprises identifying a selected failure bit as being caused by the one or more system logic defects if the selected failure bit is located on a good scan chain, on a good channel, or at a primary output, and if the simulation results corresponding to the selected failure bit do not comprise an unknown value.

41. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 38.

42. One or more computer-readable media storing a description of the one or more failing bits determined as being caused by the one or more system logic defects by the method of claim 38.

43. An electronic circuit having one or more repaired defects that were diagnosed according to the method of claim 38.