Evaluation Circuit and Method for Detecting and/or Locating Faulty Data Words in a Data Stream Tn
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Abstract
An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
17 Citations
63 Claims
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1-29. -29. (canceled)
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30. An evaluation circuit comprising:
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a first linear automation circuit; a second linear automation circuit connected in parallel with the first linear automation circuit, each having a set of states, which have a common input line for receiving a data stream, wherein the first linear automaton circuit and the second linear automation circuit are configured such that a first signature and a second signature can be calculated; a first logic combination gate and a second logic combination gate that compare the first signature and the second signature, respectively, with a predeterminable good signature and an output comparison-value. - View Dependent Claims (31, 32, 33, 34)
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35. An evaluation circuit for detecting and/or locating faulty data words in a data stream Tn comprising:
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a first linear automaton circuit and a second linear automaton circuit connected in parallel, each having a set of states, wherein the first linear automaton circuit and the second linear automaton circuit have a common input line for receiving a data stream Tn comprising n successive data words y(1), . . . , y(n) each having a width of k bits, wherein the first linear automaton circuit can be described by the following equation
z(t+1)=Az(t)⊕
y(t)wherein second linear automaton circuit can be described by the following equation
z(t+1)=Bz(t)⊕
y(t)where A and B represent the state matrices of the linear automaton circuits, where the state matrices A and B can be inverted, and where the dimension L of the state vectors is ≧
k,the first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated, L first logic combination gates arranged downstream of the first linear automaton circuit and also L second logic combination gates arranged downstream of the second linear automaton circuit, the logic combination gates are designed such that the signature respectively calculated by the linear automaton circuit can be compared with a predeterminable good signature and a comparison value can be output. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 54, 55, 56, 57, 58, 63)
or
Cod1(y′
(i))=Cod1(y(i)⊕
e(i))=Cod1(y(i)⊕
f1(e(i))where a function f1 by f1(0)=0 exists for y′
(i)=y(i)⊕
e(i), and where a function ƒ
1−
1 where
ƒ
1−
1 (f1(e))=eexists for all binary data words e having the word width k which may occur as errors of a data word, where e denotes a faulty data word of the data stream Tn.
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39. The evaluation circuit as claimed in one of claim 35, comprising wherein arranged upstream of the second linear automaton circuit is a second coder, which codes the data word y(i) having the data word length of k bits into a coded data word u2(i), u2(i)=Cod2(y(i)) having the word width of K2 bits, for i=1, . . . , n, and where Cod2 represents the coding function of the second coder.
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40. The evaluation circuit as claimed in claim 39, comprising wherein the following holds true for the coding function of the second coder:
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where a function ƒ
2−
1 where
ƒ
2−
1 (f2(e))=eexists for all binary data words e having the word width k which may occur as errors of a data word, where e denotes a faulty data word of the data stream Tn.
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41. The evaluation circuit as claimed in one of claim 37, comprising wherein that the word width K1 of the data words u1(i) coded by the first coder is equal to the word width K2 of the data words u2(i) coded by the second coder.
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42. The evaluation circuit as claimed in one of claim 37, comprising wherein the first coder matches the second coder with regard to its construction and its function.
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43. The evaluation circuit as claimed in one of claim 37, comprising wherein the word width K1 of the data words u1(i) coded by the first coder and the word width K2 of the data words u2(i) coded by the second coder are in each case equal to the word width k of the data words y(1), . . . , y(n) of the data stream Tn.
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44. The evaluation circuit as claimed in one of claim 37, comprising wherein the coding functions Cod1 and Cod2 of the first coder and of the second coder are designed as follows:
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Cod1(y1(i), y2(i), . . . , yk(i))=P1(y1(i), y2(i), . . . , yk(i), 0, . . . ,
0)
Cod2(y1(i), y2(i), . . . , yk(i))=P2(y1(i), y2(i), 0, . . . ,
0)for i, 1, . . . , n where the number of zeros situated at the end of P1(y1(i), y2(i), . . . , yk(i), 0, . . . ,
0) is equal to (K1−
k), where the number at the end of P2(y1(i), y2(i), . . . , yk(i), 0, . . . ,
0) is equal to (K2−
k), and where P1 represents an arbitrary permutation of the K1 components of (y1(i), y2(i), . . . , yk(i), 0, . . . ,0) and P2 represents an arbitrary permutation of the K2 components of (y1(i), y2(i), yk(i), 0, . . . ,0).
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45. The evaluation circuit as claimed in claim 37, comprising wherein the coding functions Cod1 and Cod2 of the first coder and of the second coder are designed as follows:
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Cod1(y1(i), y2(i), . . . , yk(i))=P1(yi(i), y2(i), . . . , yk(i), b11 . . . , bK1 k1)
Cod2(y1(i), y2(i), . . . , yk(i))=P2(y1(i), y2(i), . . . , yk(i), b12 . . . , bK2 k2)where b11, . . . , bK1−
k1, b12, . . . , bK2−
k2 ε
{0.1}, and where P1 and P2 represent arbitrary permutations.
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46. The evaluation circuit as claimed in one of claim 37, comprising wherein the coding function Cod1 of the first coder is designed such that it realizes a linear block code, f1=Cod1.
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47. The evaluation circuit as claimed in one of claim 37, comprising wherein the coding function Cod2 of the second coder is designed such that it realizes a linear block code, f2=Cod2.
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48. The evaluation circuit as claimed in one of claim 35, comprising wherein the state matrix A of the first linear automaton circuit and the state matrix B of the second linear automaton circuit are related to one another as follows:
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B=Anwhere n≠
1.
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49. The evaluation circuit as claimed in claim 35, comprising wherein the state matrix B of the second linear automaton circuit is equal to the inverted state matrix A−
- 1 of the first linear automaton circuit.
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50. The evaluation circuit as claimed in claim 35, comprising wherein the first linear automaton circuit is designed as a linear feedback shift register and the second linear automaton circuit is designed as an inverse linear feedback shift register, both linear automaton circuits having a parallel input.
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51. The evaluation circuit as claimed in claim 35, comprising wherein the first linear automaton circuit is designed as a linear feedback, K1-dimensional multi-input shift register and/or the second linear automaton circuit is designed as a linear feedback, K2-dimensional multi-input shift register.
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52. The evaluation circuit as claimed in claim 51, comprising wherein the multi-input shift register/registers has/have a primitive feedback polynomial of maximum length.
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54. The method as claimed in claim 53, comprising wherein the method is carried out by means of an evaluation circuit as claimed in one of claim 35.
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55. The evaluation circuit as claimed in one of claim 35, comprising wherein the evaluation circuit is monolithically integrated on an integrated circuit.
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56. A loadboard for receiving at least one needle card for testing integrated circuits and/or having at least one test socket for testing integrated circuits and/or for connecting a handler to a tester of integrated circuits, the loadboard having an evaluation circuit as claimed in one of claim 35.
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57. A needle card for testing integrated circuits, in which an evaluation circuit as claimed in one of claim 35 is integrated.
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58. A tester for testing integrated circuits having the following features:
the tester is provided with a plurality of instruments for generating signals or data streams and with a plurality of measuring sensors, in particular for currents and voltages, the tester has a loadboard which is provided for receiving at least one needle card for testing integrated circuits and/or for connecting a handler to a tester of integrated circuits and/or which is equipped with at least one test socket for testing integrated circuits, and the tester has an evaluation circuit as claimed in one of claim 35.
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63. A method in which a computer program as claimed in claim 57 is downloaded from an electronic data network onto a computer connected to the data network.
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53. A method for detecting and/or locating faulty data words in a data stream Tn, the method having the following method steps of:
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inputting data words y(1), . . . , y(i−
1), y′
(i), y(i+1), . . . , y(n) of a data stream Tn into a first coder,coding the data words y(1), . . . , y(n) into coded data words u1(1), . . . , u1(n) having the word width K1 where K1≧
k by means of the coding function Cod1 of the first coder,inputting the coded data words u1(1), . . . , u1(i−
1), u1′
(i) or u1(i), u1(i), . . . , u1(n) into the inputs of a first linear automaton circuit, which is described by the automaton equation;
z1(t+1)=A·
z1(t)+u1(t)where z1 represents a K1-dimensional state vector and A represents a K1×
K1 state matrix, and where the state matrix A can be inverted,processing the coded data words u1(1), . . . , u1(i−
1), u1′
(i) or u1(i), u1(i), . . . , u1(n) by means of the first linear automaton circuit, the first linear automaton circuit,undergoing transition to the state z1(n+1)=S1(L1, y(1), . . . , y(i−
1), y(i), y(i+1), . . . , y(n)) if no error can be detected in the case of the coded data words u1(1), . . . , u1(i−
1), u1(i), u1(i+1), . . . , u1(n),undergoing transition to the state z1′
(n+1)=S1(L1, y(1), . . . , y(i−
1), y′
(i), y(i+1), . . . , y(n)) if an error is present at least in the case of the i-th position of the coded data words u1(1), . . . , u1(i−
1), u1′
(i), . . . , u1(n),the signature of an error-free data stream Tn being designated by S(L1, y(1), . . . , y(i−
1), y(i), y(i+1), . . . , y(n)) and the signature of a faulty data stream Tn being designated by S(L1, y(1), . . . , y(i−
1), y′
(i), y(i+1), . . . , y(n)),checking the determined signature of the data stream Tn and continuing with method step a) for further data streams Tn if the determined signature of the data stream Tn is the signature of an error-free data stream Tn, inputting the data words y(1), . . . , y(i−
1), y′
(i), . . . , y(n) of the data stream Tn in a second coder,coding the data words y(1), . . . , y(i−
1), y′
(i), y(i+1 ), . . . , y(n) to coded data words u2(1), . . . , u2(i−
1), u2′
(i) or u2(i), u2(i), . . . , u2 (n) having the word width K2 where K2≧
k by means of the coding function Cod2 of the second coder,inputting the coded data words u2(1), . . . , u2(i−
1), u2′
(i) or u2(i), u2(i), . . . , u2(n) into the inputs of a second linear automaton circuit, which is described by the automaton equation
z2(t+1)=B·
z2(t)⊕
u2(t)where z2 represents a K2-dimensional state vector and B represents a K2×
K2 state matrix where B≠
A, and where the state matrix B can be inverted,processing the coded data words u2(1), . . . , u2(i−
1), u2′
(i) or u2(i), u2(i), . . . , u2(n) by means of the second linear automaton circuit, the second linear automaton circuit,undergoing transition to the state z2(n+1)=S2(L2, y(1), . . . , y(i−
1), y(i), y(i+1), . . . , y(n)) if no error can be detected in the case of the data words u2(1), . . . , u2(i−
1), u2(i), u2(i), . . . , u2(n),undergoing transition to the state z2′
(n+1)=S2(L2, y(1), . . . , y(i−
1), y(i), y′
(i), y(i+1), . . . , y(n)) if an error is present at least in the case of the i-th position of the coded data words u2(1), . . . , u2(i−
1), u2′
(i), u2(i), . . . , u2(n),the signature of an error-free data stream Tn being designated by S(L2, y(1), . . . , y(i−
1), y(i), y(i+1), . . . , y(n)) and the signature of a faulty data stream Tn being designated by S(L2, y(1), . . . , y(i−
1), y′
(i), . . . , y(n)),determining the signature differences Δ
S1 and Δ
S2 by means of exclusive-OR logic combinations of the signatures S1 and S2 determined in method step d) and i), respectively, with ascertained good signatures, in each case according to the following specifications;
Δ
S1=S(L1, y(1), . . . , y(i−
1), y(i), y(i+1), . . . , y(n))
⊕
S(L2, y(1), . . . , y(i−
1), y′
(i), y(i+1), . . . , y(n))
Δ
S2 =S(L2, y(1), . . . , y(i−
1), y(i), y(i+1), . . . , y(n))
⊕
S(L2, y(1), . . . y(i−
1), y′
(i), y(i+1), . . . , y(n))determining a unique solution for the position i of the faulty bit in the faulty data word by solving the equation
ƒ
1−
1(Ai−
nΔ
S1)=ƒ
2−
1(Bi−
nΔ
S2)and if no unique solution results for 1≦
i≦
n, outputting a notification by means of an output medium that two or more errors are present in the data stream Tn under consideration,determining a unique solution for the counter e(i) of the faulty data word y′
(i) in the data stream Tn by solving the equation
e(i)=ƒ
1−
1(Ai−
nΔ
S1)outputting the position i of the faulty bit in the faulty data word and also the error e(i) of the faulty data word y′
(i) in the data stream Tn by means of an output medium.- View Dependent Claims (59, 60, 61, 62)
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Specification