Semiconductor device and method for manufacturing semiconductor device

• US 20080042165A1
• Filed: 07/26/2007
• Published: 02/21/2008
• Est. Priority Date: 08/02/2006
• Status: Abandoned Application

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Sugizaki, Taro
• Application Number:
  US11/878,684
• Publication Number:
  US 20080042165A1
• Time in Patent Office: Days
• US Class Current: 257/133
• CPC Class Codes: H01L 27/0817 Thyristors only
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/7436 Lateral thyristors
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure

Abstract

A semiconductor device includes a thyristor configured to be formed through sequential joining of a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type, and have a gate formed over the third region. The first to fourth regions are formed in a silicon germanium region or germanium region.

Claims

1. A semiconductor device comprising

a thyristor configured to be formed through sequential joining of a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type, and have a gate formed over the third region, wherein

the first to fourth regions are formed in a silicon germanium region or germanium region.

2. The semiconductor device according to claim 1, wherein

the silicon germanium region or germanium region is formed of a silicon germanium layer or germanium layer formed on a semiconductor substrate.

3. A semiconductor device comprising

a thyristor configured to be formed through sequential joining of a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type, and have a gate formed over the third region, wherein

the second region is formed of a silicon germanium layer or germanium layer.

4. The semiconductor device according to claim 3, wherein

the first region is formed by introducing an impurity of the first conductivity type into the silicon germanium layer or germanium layer.

5. The semiconductor device according to claim 3, wherein

the silicon germanium layer or germanium layer is formed in a recess formed in a silicon semiconductor region in which the third region is formed.

6. The semiconductor device according to claim 5, wherein

the first region is formed on the second region.

7. The semiconductor device according to claim 3, wherein

the second region is formed on a silicon semiconductor region in which the third region is formed.

8. The semiconductor device according to claim 7, wherein

the first region is formed on the second region.

9. The semiconductor device according to claim 3, wherein

the first region is formed in a recess formed in the second region.

10. The semiconductor device according to claim 3, wherein

the second region is formed of a silicon germanium layer formed on a silicon semiconductor region, and a part in the second region closer to the silicon semiconductor region has a higher composition ratio of germanium.

11. A method for manufacturing a semiconductor device that includes a thyristor formed through sequential joining of a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type, the thyristor having a gate formed over the third region, the method comprising the step of:

forming the first to fourth regions in a silicon germanium region or germanium region.

12. The method for manufacturing a semiconductor device according to claim 11, wherein

the silicon germanium region or germanium region is formed on a semiconductor substrate by epitaxial growth.

13. A method for manufacturing a semiconductor device that includes a thyristor formed through sequential joining of a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type, the thyristor having a gate formed over the third region, the method comprising the step of:

forming the second region by using a silicon germanium layer or germanium layer.

14. The method for manufacturing a semiconductor device according to claim 13, wherein

the first region is formed by introducing an impurity of the first conductivity type into the silicon germanium layer or germanium layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein

the silicon germanium layer or germanium layer is formed by forming a recess in a silicon semiconductor region in which the third region is formed and growing silicon germanium or germanium in the recess by epitaxial growth.

16. The method for manufacturing a semiconductor device according to claim 15, wherein

the first region is formed on the second region.

17. The method for manufacturing a semiconductor device according to claim 13, wherein

the second region is formed on a silicon semiconductor region in which the third region is formed.

18. The method for manufacturing a semiconductor device according to claim 17, wherein

the first region is formed on the second region.

19. The method for manufacturing a semiconductor device according to claim 13, wherein

the first region is formed by forming a recess in the second region and growing silicon germanium or germanium in the recess by epitaxial growth.

20. The method for manufacturing a semiconductor device according to claim 13, wherein

the second region is formed on a silicon semiconductor region by using a silicon germanium layer in such a way that a part in the second region closer to the silicon semiconductor region has a higher composition ratio of germanium.