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Memory arrays and methods of fabricating memory arrays

  • US 20080042179A1
  • Filed: 08/21/2006
  • Published: 02/21/2008
  • Est. Priority Date: 08/21/2006
  • Status: Active Grant
First Claim
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1. A memory array comprising:

  • a plurality of memory cells formed on a semiconductor substrate, individual of the memory cells comprising;

    first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions;

    the gates being received within openings formed within semiconductive material of the substrate, one of the pair of source/drain regions being received laterally intermediate the gates and shared by the first and second transistors, each of the other of the pair of source/drain regions of the first and second transistors being received laterally outward of their respective gate;

    a conductive data line received elevationally outward of the gates and electrically connecting with each of the other of the pair of source/drain regions; and

    a charge storage device electrically connecting with the shared source/drain region.

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