Memory arrays and methods of fabricating memory arrays
First Claim
Patent Images
1. A memory array comprising:
- a plurality of memory cells formed on a semiconductor substrate, individual of the memory cells comprising;
first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions;
the gates being received within openings formed within semiconductive material of the substrate, one of the pair of source/drain regions being received laterally intermediate the gates and shared by the first and second transistors, each of the other of the pair of source/drain regions of the first and second transistors being received laterally outward of their respective gate;
a conductive data line received elevationally outward of the gates and electrically connecting with each of the other of the pair of source/drain regions; and
a charge storage device electrically connecting with the shared source/drain region.
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Abstract
A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.
145 Citations
48 Claims
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1. A memory array comprising:
a plurality of memory cells formed on a semiconductor substrate, individual of the memory cells comprising; first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions;
the gates being received within openings formed within semiconductive material of the substrate, one of the pair of source/drain regions being received laterally intermediate the gates and shared by the first and second transistors, each of the other of the pair of source/drain regions of the first and second transistors being received laterally outward of their respective gate;a conductive data line received elevationally outward of the gates and electrically connecting with each of the other of the pair of source/drain regions; and a charge storage device electrically connecting with the shared source/drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A memory array comprising:
a plurality of memory cells formed on a semiconductor substrate, individual of the memory cells comprising; first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions;
one of the pair of source/drain regions being received laterally intermediate the gates and shared by the first and second transistors, each of the other of the pair of source/drain regions of the first and second transistors being received laterally outward of their respective gate, each channel region comprising a current path in at least one cross section extending between the shared source/drain region and the respective other source/drain region which comprises interconnected first and second substantially vertical segments;a conductive data line electrically connecting with each of the other of the pair of source/drain regions; and a charge storage device electrically connecting with the shared source/drain region. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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23. A memory array comprising:
a plurality of memory cells formed on a semiconductor substrate, individual of the memory cells comprising; first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions;
one of the pair of source/drain regions being received laterally intermediate the gates and shared by the first and second transistors, each of the other of the pair of source/drain regions of the first and second transistors being received laterally outward of their respective gate, conductive material electrically interconnecting the gates of the first and second transistors;a conductive data line electrically connecting with each of the other of the pair of source/drain regions; and a charge storage device electrically connecting with the shared source/drain region. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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30. A memory array comprising:
a plurality of memory cells formed on bulk semiconductor substrate, individual of the memory cells comprising; first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions;
the gates being received within trenches formed within bulk semiconductive material of the substrate, one of the pair of source/drain regions being received within bulk semiconductive material laterally intermediate the gates and shared by the first and second transistors, each of the other of the pair of source/drain regions of the first and second transistors being received within bulk semiconductive material and laterally outward of their respective gate, conductive material electrically interconnecting the gates of the first and second transistors, each channel region comprising a current path within bulk semiconductive material in at least one cross section extending between the shared source/drain region and the respective other source/drain region which comprises interconnected first and second substantially vertical segments;a conductive data line received elevationally outward of the gates and electrically connecting with each of the other of the pair of source/drain regions; and a charge storage device electrically connecting with the shared source/drain region and received elevationally outward of the conductive data line. - View Dependent Claims (31, 32)
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33. A memory array comprising:
a plurality of memory cells formed on a semiconductor substrate, individual of the memory cells comprising; first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions;
the gates of the first and second field effect transistors being hard wired together;a conductive data line hard wired to two of the source/drain regions; and a charge storage device hard wired to at least one of the source/drain regions other than the two. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40)
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41. A method of fabricating a memory array, comprising:
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forming alternating lines of active area regions and trench isolation regions within a semiconductor substrate; etching a series of racetrack-shaped trenches into the active area regions and the trench isolation regions generally orthogonal to the alternating lines of active area regions and trench isolation regions; forming conductive material within the racetrack-shaped trenches to form a pair of electrically connected word lines with respect to individual of the racetrack-shaped trenches; forming source/drain regions within the active area regions laterally internal of the racetrack-shaped trenches and laterally external of the racetrack-shaped trenches; forming conductive data lines in electrical connection with the source/drain regions received laterally external of the racetrack-shaped trenches; and forming a charge storage device in electrical connection with respective of the source/drain regions received laterally internal of the racetrack-shaped trenches.
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42. A method of fabricating a memory array, comprising:
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forming alternating lines of active area regions and trench isolation regions within a semiconductor substrate; etching a series of pairs of trenches into the active area regions and the trench isolation regions generally orthogonal to the alternating lines of active area regions and trench isolation regions; etching at least one interconnecting trench into the semiconductor substrate which interconnects individual of the trenches of each pair; forming conductive material within the pairs of trenches and the interconnecting trench to form a pair of electrically connected word lines with respect to individual of the pairs; forming source/drain regions within the active area regions intermediate individual of the trenches of each pair and laterally external of individual of the trenches of each pair; forming conductive data lines in electrical connection with the source/drain regions received laterally external of individual of the trenches of each pair; and forming a charge storage device in electrical connection with respective of the source/drain regions received intermediate individual of the trenches of each pair. - View Dependent Claims (43, 44, 45, 46, 47, 48)
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Specification