TRENCH MOSFET WITH TERRACED GATE AND MANUFACTURING METHOD THEREOF

• US 20080042194A1
• Filed: 05/16/2007
• Published: 02/21/2008
• Est. Priority Date: 08/16/2006
• Status: Active Grant

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hshieh, FWU-IUAN
• Granted Patent: US 7,629,646 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced trench gate. An epitaxial layer with a plurality of trenches is provided and a gate oxide layer is covered the sidewalls and bottoms of the trenches. A polysilicon layer is filled in the trenches, wherein the polysilicon layer is higher than the sidewalls of the trenches to be used as a gate of the MOSFET. A plurality of sources and bodies are formed in the epitaxial layer, and the bodies at both sides of the trenches. An insulating layer is covered on the substrate, wherein a plurality of metal contact windows are provided. Metal plugs are filled in the metal contact windows to form metal connections for the MOSFET.

Claims

1. A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced gate, comprising:

a plurality of trenches formed on top of epitaxial layer;

a gate oxide layer formed on the sidewalls and bottom of the trenches;

a polysilicon layer filled in the trenches, wherein the polysilicon layer protruding out of the trenches is higher than the sidewalls of the trenches to be used as a gate of the MOSFET;

a plurality of sources and bodies formed in the epitaxial layer, and bodies at both sides of the trenches;

an insulating layer deposited on the epitaxial layer formed with a plurality of metal contact holes therein for contacting respective source and body regions; and

metal plugs filled in the metal contact windows to form metal connections for the MOSFET.

2. The MOSFET of claim 1, wherein one of the metal contact windows is provided on the gate as a metal connection for the gate.

3. The MOSFET of claim 2, wherein the metal contact window avoids polysilicon seam regions in the middle of gate by connecting to a side of the gate.

4. The MOSFET of claim 1, wherein the metal contact windows are provided on the sources as metal connections for the sources.

5. The MOSFET of claim 1, wherein the metal plugs are made of tungsten metal materials surrounding with barrier metals.

6. The transistor of claim 1, wherein the gate oxide layer in trench gates is single oxide of which oxide thickness nearly uniform along trench sidewall and bottom.

7. The transistor of claim 1, wherein the gate oxide layer at the bottoms of trench gates has a significant larger thickness than trench sidewall so as to reduce the capacitance of the gate oxide layer.

8. A method for manufacturing a trench MOSFET with a terraced gate, comprising:

providing an epitaxial on substrate with a thick oxide on the top;

a plurality of trenches is formed through dry etching the thick oxide and silicon;

providing a gate oxide layer covered the sidewalls and bottoms of the trenches;

providing a polysilicon layer filled in the trenches, wherein the polysilicon layer is higher than the sidewalls of the trenches to be used as a gate of the MOSFET;

removing a part of the oxide layer above silicon mesa that is substantially outside the trenches;

forming a plurality of sources and bodies formed in the epitaxial layer, and the bodies at both sides of the trenches;

forming an insulating layer covered on the epitaxial layer, wherein a plurality of metal contact windows are provided; and

forming metal plugs filled in the metal contact windows to form metal connections for the MOSFET.

9. The method of claim 8, wherein one of the metal contact windows is provided on the gate as a metal connection for the gate.

10. The method of claim 9, wherein the metal contact window avoids polysilicon seam regions in the middle of gate by connecting to a side of the gate.

11. The method of claim 8, wherein the metal contact windows are provided on the sources as metal connections for the sources.

12. The method of claim 8, wherein the metal plugs are made of tungsten metal materials.

13. The transistor of claim 8, wherein the gate oxide layer in trench gates is single oxide of which oxide thickness nearly uniform along trench sidewall and bottom.

14. The method of claim 8, wherein the thickness of the gate oxide layer on the bottom of the gate is larger than that on the sidewalls of the trenches.