High performance system-on-chip using post passivation process
First Claim
Patent Images
1. An integrated circuit chip comprising:
- a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost oxide layer of said integrated circuit chip and a topmost nitride layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer;
a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers and greater than those of said passivation layer and said first and second dielectric layers;
a coil on said first polymer layer, wherein said coil comprises an electroplated metal layer, and wherein said coil has a thickness greater than those of said first and second metal layers;
a metal line on said first polymer layer, wherein said metal line has a thickness greater than those of said first and second metal layers, wherein said metal line and said coil are separate from each other; and
a second polymer layer over said metal line.
5 Assignments
0 Petitions
Accused Products
Abstract
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
121 Citations
25 Claims
-
1. An integrated circuit chip comprising:
-
a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost oxide layer of said integrated circuit chip and a topmost nitride layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer;
a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers and greater than those of said passivation layer and said first and second dielectric layers;
a coil on said first polymer layer, wherein said coil comprises an electroplated metal layer, and wherein said coil has a thickness greater than those of said first and second metal layers;
a metal line on said first polymer layer, wherein said metal line has a thickness greater than those of said first and second metal layers, wherein said metal line and said coil are separate from each other; and
a second polymer layer over said metal line. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. An integrated circuit chip comprising:
-
a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, a first passivation opening in said passivation layer exposing a first pad of said metallization structure, and a second passivation opening in said passivation layer exposing a second pad of said metallization structure, wherein said first and second pads are separate from each other, wherein said passivation layer comprises a topmost oxide layer of said integrated circuit chip and a topmost nitride layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer;
a first polymer layer over said passivation layer, a first polymer opening in said first polymer layer exposing said first pad, and a second polymer opening in said first polymer layer exposing said second pad, wherein said first polymer layer has a thickness between 2 and 150 micrometers and greater than those of said passivation layer and said first and second dielectric layers;
a coil over said first polymer layer, wherein said coil is connected to said first pad through said first polymer opening and said first passivation opening, wherein said coil comprises electroplated copper, and wherein said coil has a thickness greater than those of said first and second metal layers;
a metal line on said first polymer layer, wherein said metal line is connected to said second pad through said second polymer opening and said second passivation opening, and wherein said metal line has a thickness greater than those of said first and second metal layers, and wherein said metal line and said coil are separate from each other; and
a second polymer layer over said metal line. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. An integrated circuit chip comprising:
-
a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost oxide layer of said integrated circuit chip and a topmost nitride layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer;
a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers and greater than those of said passivation layer and said first and second dielectric layers;
a coil on said first polymer layer, wherein said coil comprises a gold layer, and wherein said coil has a thickness greater than those of said first and second metal layers;
a metal line on said first polymer layer, wherein said metal line has a thickness greater than those of said first and second metal layers, and wherein said metal line and said coil are separate from each other; and
a second polymer layer over said metal line. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25)
-
Specification