High performance system-on-chip using post passivation process
First Claim
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1. An integrated circuit chip comprising:
- a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, a passivation opening in said passivation layer exposing a pad of said metallization structure, wherein said passivation layer comprises an oxide layer and a nitride layer, wherein said nitride layer is over said oxide layer;
a polymer layer over said passivation layer, a polymer opening in said polymer layer exposing said pad, wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than those of said passivation layer and said first and second dielectric layers; and
a capacitor on said polymer layer, wherein said capacitor comprises a lower plate on said polymer layer, wherein said lower plate comprises a first conductive layer and has a thickness between 0.5 and 20 micrometers, and wherein said lower plate connects to said pad through said polymer opening and said passivation opening, a third dielectric layer on said lower plate, and an upper plate on said third dielectric layer, wherein said upper plate comprises a second conductive layer and has a thickness between 0.5 and 20 micrometers.
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Abstract
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
116 Citations
18 Claims
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1. An integrated circuit chip comprising:
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a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, a passivation opening in said passivation layer exposing a pad of said metallization structure, wherein said passivation layer comprises an oxide layer and a nitride layer, wherein said nitride layer is over said oxide layer;
a polymer layer over said passivation layer, a polymer opening in said polymer layer exposing said pad, wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than those of said passivation layer and said first and second dielectric layers; and
a capacitor on said polymer layer, wherein said capacitor comprises a lower plate on said polymer layer, wherein said lower plate comprises a first conductive layer and has a thickness between 0.5 and 20 micrometers, and wherein said lower plate connects to said pad through said polymer opening and said passivation opening, a third dielectric layer on said lower plate, and an upper plate on said third dielectric layer, wherein said upper plate comprises a second conductive layer and has a thickness between 0.5 and 20 micrometers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit chip comprising:
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a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, a passivation opening in said passivation layer exposing a pad of said metallization structure, wherein said passivation layer comprises a oxide layer and a nitride layer, wherein said nitride layer is over said oxide layer;
a polymer layer over said passivation layer, a polymer opening in said polymer layer exposing said pad, wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than those of said passivation layer and said first and second dielectric layers; and
a resistor on said polymer layer, wherein said resistor comprises a resistive material layer on said polymer layer, wherein said resistor connects to said pad through said polymer opening and said passivation opening. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification