Post passivation interconnection schemes on top of IC chip

• US 20080042285A1
• Filed: 09/17/2007
• Published: 02/21/2008
• Est. Priority Date: 10/18/2000
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Granted Patent: US 8,482,127 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A chip comprising:

a silicon substrate;

a first internal circuit in or on said silicon substrate;

a second internal circuit in or on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises nitride and oxide, and wherein one of multiple openings in said passivation layer has a diameter between 0.5 and 30 micrometers;

a first via in one of said multiple openings, wherein said first via is connected to said first interconnecting structure;

a second via in one of said multiple openings, wherein said second via is connected to said second interconnecting structure; and

a clock bus over said passivation layer, wherein said clock bus is connected to said first and second vias, and wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.

2. The chip of claim 1 further comprising a third internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said third internal circuit, wherein said first internal circuit is connected to said third internal circuit through said first interconnecting structure, and wherein said third internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.

3. The chip of claim 2 further comprising a fourth internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said fourth internal circuit, wherein said second internal circuit is connected to said fourth internal circuit through said second interconnecting structure, and wherein said first and third internal circuits are connected to said fourth internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.

4. The chip of claim 2 further comprising a fourth internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said fourth internal circuit, wherein said first and third internal circuits are connected to said fourth internal circuit through said first interconnecting structure, and wherein said fourth internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.

5. The chip of claim 1 further comprising a driver, receiver or I/O circuit in or on said silicon substrate, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit, and a third via in one of said multiple openings, wherein said third via is connected to said third interconnecting structure and to said clock bus, wherein said first terminal is connected to said first internal circuit through, in sequence, said third interconnecting structure, said third via, said clock bus, said first via and said first interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said third interconnecting structure, said third via, said clock bus, said second via and said second interconnecting structure.

6. The chip of claim 5 further comprising an ESD circuit in or on said silicon substrate and a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said ESD circuit is connected to a second terminal of said driver, receiver or I/O circuit through said fourth interconnecting structure.

7. The chip of claim 1 further comprising a polymer layer over said passivation layer, wherein said clock bus is in said polymer layer.

8. The chip of claim 7, wherein said polymer layer has a thickness of greater than 2 micrometers.

9. The chip of claim 1, wherein said clock bus has a thickness greater than 1 micrometer.

10. A chip comprising:

a silicon substrate;

a first internal circuit in or on said silicon substrate;

a second internal circuit in or on said silicon substrate;

a dielectric system over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric system, wherein said first interconnecting structure is connected to said first internal circuit;

a second interconnecting structure over said silicon substrate and in said dielectric system, wherein said second interconnecting structure is connected to said second internal circuit;

multiple metal layers in said dielectric system, wherein said dielectric system comprises multiple dielectric layers between said multiple metal layers;

a passivation layer over said dielectric system and over said multiple metal layers, wherein said passivation layer comprises nitride and oxide;

a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;

a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and

a clock bus over said passivation layer, wherein said clock bus has a thickness greater than 1 micrometer and greater than those of said multiple metal layers, wherein said clock bus is connected to said first and second vias, and wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.

11. The chip of claim 10 further comprising a third internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said third internal circuit, wherein said first internal circuit is connected to said third internal circuit through said first interconnecting structure, and wherein said third internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.

12. The chip of claim 11 further comprising a fourth internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said fourth internal circuit, wherein said second internal circuit is connected to said fourth internal circuit through said second interconnecting structure, and wherein said first and third internal circuits are connected to said fourth internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.

13. The chip of claim 11 further comprising a fourth internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said fourth internal circuit, wherein said first and third internal circuits are connected to said fourth internal circuit through said first interconnecting structure, and wherein said fourth internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.

14. The chip of claim 10 further comprising a driver, receiver or I/O circuit in or on said silicon substrate, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit, and a third via in said passivation layer, wherein said third via is connected to said third interconnecting structure and to said clock bus, wherein said first terminal is connected to said first internal circuit through, in sequence, said third interconnecting structure, said third via, said clock bus, said first via and said first interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said third interconnecting structure, said third via, said clock bus, said second via and said second interconnecting structure.

15. The chip of claim 14 further comprising an ESD circuit in or on said silicon substrate and a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said ESD circuit is connected to a second terminal of said driver, receiver or I/O circuit through said fourth interconnecting structure.

16. The chip of claim 10 further comprising a polymer layer over said passivation layer, wherein said clock bus is in said polymer layer.

17. The chip of claim 16, wherein said polymer layer has a thickness of greater than 2 micrometers.