VOLTAGE BUFFER AND SOURCE DRIVER THEREOF

• US 20080042689A1
• Filed: 10/30/2006
• Published: 02/21/2008
• Est. Priority Date: 08/15/2006
• Status: Active Grant

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Yen, Chin-Jen
• Granted Patent: US 7,518,415 B2
• Time in Patent Office: Days
• US Class Current: 326/82
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A voltage buffer and the source driver thereof are disclosed. The above-mentioned voltage buffer includes an operational amplifier and an overdriving unit, wherein the operational amplifier outputs an output voltage. The overdriving unit is coupled between an input voltage and the operational amplifier for comparing the input voltage with the output voltage and outputting an overdriving voltage to the positive input terminal of the operational amplifier. Herein if the input voltage is greater than the output voltage, the overdriving voltage is greater than the input voltage; if the input voltage is less than the output voltage, the overdriving voltage is less than the input voltage; if the input voltage is equal to the output voltage, the overdriving voltage is equal to the input voltage.

Claims

1. A voltage buffer, comprising:

an operational amplifier, having a positive input terminal, a negative input terminal and an output terminal, wherein the output terminal is coupled to the negative input terminal and outputs an output voltage; and

an overdriving unit, coupled between an input voltage and the operational amplifier for comparing the input voltage with the output voltage and outputting an overdriving voltage to the positive input terminal of the operational amplifier;

wherein if the input voltage is greater than the output voltage, the overdriving unit makes the overdriving voltage greater than the input voltage;

if the input voltage is less than the output voltage, the overdriving unit makes the overdriving voltage less than the input voltage;

if the input voltage is equal to the output voltage, the overdriving voltage is equal to the input voltage.

2. The voltage buffer according to claim 1, wherein the overdriving unit comprises:

a voltage detector, used for comparing the input voltage with the output voltage and outputting a voltage-increasing signal and a voltage-decreasing signal;

a control unit, coupled to the voltage detector and outputting a control signal according to the voltage-increasing signal and the voltage-decreasing signal; and

a voltage-regulating circuit, coupled to the control unit and regulating the level of the overdriving voltage according to the control signal output from the control unit.

3. The voltage buffer according to claim 2, wherein the voltage detector comprises:

a first PMOS transistor, being serially connected to a first NMOS transistor, and the first PMOS transistor and the first NMOS transistor are coupled between a first operation voltage and a first current source, wherein the gate of the first NMOS transistor is coupled to the input voltage;

a second PMOS transistor, being serially connected to a second NMOS transistor, and the second PMOS transistor and the second NMOS transistor are coupled between the first operation voltage and the first current source, wherein the gate of the second NMOS transistor is coupled to the output voltage, the gate of the second PMOS transistor is coupled to the gate of the first PMOS transistor and the gate of the second PMOS transistor is coupled to the common node of the second PMOS transistor and the second NMOS transistor;

a second current source, being serially connected to a third NMOS transistor, and the second current source and the third NMOS transistor are coupled between the first operation voltage and a second operation voltage, wherein the gate of the third NMOS transistor is coupled to the common node of the first PMOS transistor and the first NMOS transistor, and the common node of the second current source and the third NMOS transistor outputs the voltage-decreasing signal; and

a third PMOS transistor, being serially connected to a third current source, and the third PMOS transistor and the third current source are coupled between the first operation voltage and the second operation voltage, wherein the gate of the third PMOS transistor is coupled to the common node of the first PMOS transistor and the first NMOS transistor, and the common node of the third PMOS transistor and the third current source outputs the voltage-increasing signal.

4. The voltage buffer according to claim 2, wherein the voltage detector comprises:

a first PMOS transistor, being serially connected to a first NMOS transistor, and the first PMOS transistor and the first NMOS transistor are coupled between a first current source and a second operation voltage, wherein the gate of the first PMOS transistor is coupled to the input voltage;

a second PMOS transistor, being serially connected to a second NMOS transistor, and the second PMOS transistor and the second NMOS transistor are coupled between the first current source and the second operation voltage, wherein the gate of the second PMOS transistor is coupled to the output voltage, the gate of the second NMOS transistor is coupled to the gate of the first NMOS transistor and the gate of the second NMOS transistor is coupled to the common node of the second PMOS transistor and the second NMOS transistor;

a second current source, being serially connected to a third NMOS transistor, and the second current source and the third NMOS transistor are coupled between a first operation voltage and the second operation voltage, wherein the gate of the third NMOS transistor is coupled to the common node of the first PMOS transistor and the first NMOS transistor, and the common node of the second current source and the third NMOS transistor outputs the voltage-decreasing signal; and

a third PMOS transistor, being serially connected to a third current source, and the third PMOS transistor and the third current source are coupled between the first operation voltage and the second operation voltage, wherein the gate of the third PMOS transistor is coupled to the common node of the first PMOS transistor and the first NMOS transistor, and the common node of the third PMOS transistor and the third current source outputs the voltage-increasing signal.

5. The voltage buffer according to claim 2, wherein the voltage detector comprises:

a first NMOS transistor, wherein both the gate of the first NMOS transistor and the gate of a first PMOS transistor are coupled to the output voltage;

a second NMOS transistor, wherein both the gate of the second NMOS transistor and the gate of a second PMOS transistor are coupled to the input voltage;

a first current source, coupled to the source of the first PMOS transistor and the source of the second PMOS transistor;

a second current source, coupled to the source of the first NMOS transistor and the source of the second NMOS transistor;

a third PMOS transistor, coupled between a first operation voltage and the drain of the first NMOS transistor;

a fourth PMOS transistor, coupled between the first operation voltage and the drain of the second NMOS transistor, wherein both the gate of the fourth PMOS transistor and the gate of the third PMOS transistor are coupled to a first bias voltage;

a fifth PMOS transistor, wherein the source of the fifth PMOS transistor is coupled to the drain of the third PMOS transistor;

a sixth PMOS transistor, wherein the source of the sixth PMOS transistor is coupled to the drain of the fourth PMOS transistor, and both the gate of the sixth PMOS transistor and the gate of the fifth PMOS transistor are coupled to a second bias voltage;

a third NMOS transistor, wherein the drain of the third NMOS transistor is coupled to the drain of the fifth PMOS transistor, and the source of the third NMOS transistor is coupled to the drain of the first PMOS transistor;

a fourth NMOS transistor, wherein the drain of the fourth NMOS transistor is coupled to the drain of the sixth PMOS transistor, both the gate of the fourth NMOS transistor and the gate of the third NMOS transistor are coupled to a third bias voltage, and the source of the fourth NMOS transistor is coupled to the drain of the second PMOS transistor;

a fifth NMOS transistor, coupled between the source of the third NMOS transistor and a second operation voltage, wherein the gate of the fifth NMOS transistor is coupled to the drain of the third NMOS transistor;

a sixth NMOS transistor, coupled between the source of the fourth NMOS transistor and the second operation voltage, wherein the gate of the sixth NMOS transistor is coupled to the gate of the fifth NMOS transistor;

a seventh NMOS transistor, coupled between a third current source and the second operation voltage, wherein the gate of the seventh NMOS transistor is coupled to the common node of the sixth PMOS transistor and the fourth NMOS transistor;

a seventh PMOS transistor, coupled between the first operation voltage and a fourth current source, wherein the gate of the seventh PMOS transistor is coupled to the common node of the sixth PMOS transistor and the fourth NMOS transistor;

wherein the common node of the seventh NMOS transistor and the third current source outputs the voltage-decreasing signal, while the common node of the seventh PMOS transistor and the fourth current source outputs the voltage-increasing signal.

6. The voltage buffer according to claim 2, wherein the operational amplifier comprises a differential amplifier and an output-stage circuit, the differential amplifier outputs a differential signal to the output-stage circuit according to the signals received by the positive input terminal and the negative input terminal, and the voltage detector comprises:

an NMOS transistor, coupled between a first current source and a second operation voltage, wherein the gate of the NMOS transistor is coupled to the output terminal of the differential amplifier; and

a PMOS transistor, coupled between a first operation voltage and a second current source, wherein the gate of the PMOS transistor is coupled to the output terminal of the differential amplifier;

wherein the common node of the NMOS transistor and the first current source outputs the voltage-decreasing signal, while the common node of the PMOS transistor and the second current source outputs the voltage-increasing signal.

7. The voltage buffer according to claim 2, wherein the control unit outputs a charging signal, a first path signal, a second path signal and a restoration signal for regulating the output of the voltage-regulating circuit, and the control unit comprises:

a clock-regulating circuit, outputting the charging signal and a reference signal according to a clock signal;

a first control circuit, outputting the first path signal according to the voltage-increasing signal and the reference signal;

a second control circuit, outputting the second path signal according to the voltage-decreasing signal and the reference signal; and

a restoration circuit, outputting the restoration signal according to the voltage-increasing signal, the voltage-decreasing signal and the reference signal.

8. The voltage buffer according to claim 7, wherein the clock-regulating circuit comprises:

a delay circuit, used for delaying the clock signal and outputting a delayed clock signal;

an NOR gate, coupled to the delay circuit and outputting the reference signal according to the delayed clock signal and the clock signal; and

an NAND gate, coupled to the delay circuit and outputting the charging signal via an inverter according to the delayed clock signal and the clock signal.

9. The voltage buffer according to claim 8, wherein the delay circuit comprises an even number of inverters.

10. The voltage buffer according to claim 7, wherein the first control circuit comprises:

an NAND gate, wherein an input terminal of the NAND gate is coupled to the voltage-increasing signal, while another input terminal of the NAND gate is coupled to the reference signal; and

an inverter, wherein the input terminal of the inverter is coupled to the output terminal of the NAND gate and the inverter outputs the first path signal.

11. The voltage buffer according to claim 7, wherein the second control circuit comprises:

a first inverter, wherein the input terminal of the first inverter is coupled to the voltage-decreasing signal;

an NAND gate, wherein an input terminal of the NAND gate is coupled to the output terminal of the first inverter, while another input terminal of the NAND gate is coupled to the reference signal; and

a second inverter, wherein the input terminal of the second inverter is coupled to the output terminal of the NAND gate and outputs the second path signal.

12. The voltage buffer according to claim 7, wherein the restoration circuit comprises:

a first inverter, wherein the input terminal of the first inverter is coupled to the voltage-increasing signal;

an NAND gate, having three input terminals coupled to the output terminal of the first inverter, the voltage-decreasing signal and the reference signal, respectively; and

a second inverter, wherein the input terminal of the second inverter is coupled to the output terminal of the NAND gate and the second inverter outputs the restoration signal.

13. The voltage buffer according to claim 7, wherein the voltage-regulating circuit comprises:

a capacitor, having a first terminal and a second terminal;

a first switch, coupled between a charging voltage and the first terminal of the capacitor;

a second switch, coupled between the second terminal of the capacitor and a ground terminal;

a third switch, coupled between the second terminal of the capacitor and the input voltage;

a fourth switch, coupled between the first terminal of the capacitor and the positive input terminal of the operational amplifier;

a fifth switch, coupled between the input voltage and the first terminal of the capacitor;

a sixth switch, coupled between the second terminal of the capacitor and the positive input terminal of the operational amplifier; and

a seventh switch, coupled between the positive input terminal of the operational amplifier and the input voltage;

wherein if the charging signal is enabled, the first switch and the second switch are on;

if the first path signal is enabled, the third switch and the fourth switch are on;

if the second path signal is enabled, the fifth switch and the sixth switch are on;

if the restoration signal is enabled, the seventh switch is on.

14. The voltage buffer according to claim 13, wherein the charging signal is enabled during a charging duration;

if the charging voltage is greater than the output voltage, the first path signal is enabled during an overdriving duration;

if the input voltage is less than the output voltage, the second path signal is enabled during the overdriving duration;

the overdriving duration is after the charging duration.

15. The voltage buffer according to claim 14, wherein after the overdriving duration, the restoration signal is enabled during a restoration duration.

16. The voltage buffer according to claim 13, wherein the charging signal is enabled during a charging duration;

if the charging signal is enabled, the seventh switch is on;

if the input voltage is greater than the output voltage, the first path signal is enabled during an overdriving duration;

if the input voltage is less than the output voltage, the second path signal is enabled during the overdriving duration;

the overdriving duration is after the charging duration.

17. The voltage buffer according to claim 16, wherein after the overdriving duration, the restoration signal is enabled during a restoration duration, and if the restoration signal is enabled, the first switch and the second switch are either on or off.

18. The voltage buffer according to claim 7, wherein when the charging signal is logic high, the charging signal is enabled;

when the first path signal is logic high, the first path signal is enabled;

when the second path signal is logic high, the second path signal is enabled;

when the restoration signal is logic high, the restoration signal is enabled.

19. The voltage buffer according to claim 2, wherein the control unit outputs a first path signal, a second path signal and a restoration signal for regulating the output of the voltage-regulating circuit, and the control unit comprises:

a first inverter, used for inverting the voltage-increasing signal and outputting an inverted voltage-increasing signal;

an AND gate, used for generating the restoration signal according to the voltage-decreasing signal and the inverted voltage-increasing signal; and

a second inverter, used for inverting the voltage-decreasing signal and outputting the second path signal;

wherein the control unit directly outputs the first path signal according to the voltage-increasing signal.

20. The voltage buffer according to claim 19, wherein the voltage-regulating circuit comprises:

a capacitor, having a first terminal and a second terminal;

a first switch, coupled between a charging voltage and the first terminal of the capacitor;

a second switch, coupled between the second terminal of the capacitor and a ground terminal;

a third switch, coupled between the second terminal of the capacitor and the input voltage;

a fourth switch, coupled between the first terminal of the capacitor and the positive input terminal of the operational amplifier;

a fifth switch, coupled between the input voltage and the first terminal of the capacitor;

a sixth switch, coupled between the second terminal of the capacitor and the positive input terminal of the operational amplifier; and

a seventh switch, coupled between the positive input terminal of the operational amplifier and the input voltage;

wherein if the first path signal is enabled, the third switch and the fourth switch are on;

if the second path signal is enabled, the fifth switch and the sixth switch are on;

if the restoration signal is enabled, the first switch, the second switch and the seventh switch are on.

21. The voltage buffer according to claim 20, wherein if the input voltage is greater than the output voltage, the first path signal is enabled during an overdriving duration;

if the input voltage is less than the output voltage, the second path signal is enabled during the overdriving duration.

22. The voltage buffer according to claim 21, wherein after the overdriving duration, the restoration signal is enabled during a restoration duration.

23. The voltage buffer according to claim 19, wherein the voltage-regulating circuit comprises:

a first resistor, coupled between a first current source and the input voltage, wherein another terminal of the first current source is coupled to a first operation voltage;

a second resistor, coupled between the input voltage and a second current source, wherein another terminal of the second current source is coupled to a second operation voltage;

a first switch, wherein a terminal of the first switch is coupled to the common node of the first resistor and the first current source, while another terminal of the first switch is coupled to the positive input terminal of the operational amplifier;

a second switch, wherein a terminal of the second switch is coupled to the common node of the second resistor and the second current source, while another terminal of the second switch is coupled to the positive input terminal of the operational amplifier; and

a third switch, coupled between the positive input terminal of the operational amplifier and the input voltage;

wherein if the first path signal is enabled, the first switch is on;

if the second path signal is enabled, the second switch is on;

if the restoration signal is enabled, the third switch is on.

24. The voltage buffer according to claim 19, wherein when the inverted voltage-decreasing signal is logic high, the second path signal is enabled;

when the voltage-increasing signal is logic high, the first path signal is enabled;

when the restoration signal is logic high, the restoration signal is enabled.

25. The voltage buffer according to claim 23, wherein the first operation voltage is greater than or equal to a system operation voltage.

26. The voltage buffer according to claim 23, wherein the second operation voltage is less than or equal to a system ground voltage.

27. The voltage buffer according to claim 2, wherein if the input voltage is greater than the output voltage, the voltage-increasing signal is logic high and the voltage-decreasing signal is logic high.

28. The voltage buffer according to claim 2, wherein if the input voltage is less than the output voltage, the voltage-increasing signal is logic low and the voltage-decreasing signal is logic low.

29. The voltage buffer according to claim 2, wherein if the input voltage is equal to the output voltage, the voltage-increasing signal is logic low and the voltage-decreasing signal is logic high.

30. A source driver, used for driving an LCD panel, the source driver comprising:

a driving unit, generating a plurality of first driving voltages according to an input display signal; and

a plurality of voltage buffers, coupled to the driving unit and outputting a plurality of second driving voltages according to the first driving voltages;

wherein each of the voltage buffers has an operational amplifier and an overdriving unit, the overdriving unit outputs an overdriving voltage to the operational amplifier according to the corresponding first driving voltage, and each of the voltage buffers regulates the corresponding second driving voltage according to the corresponding overdriving voltage for driving the LCD panel.

31. The source driver according to claim 30, wherein the operational amplifier has a positive input terminal, a negative input terminal and an output terminal, the output terminal is coupled to the negative input terminal, and the output terminal outputs the second driving voltage.

32. The source driver according to claim 30, wherein the overdriving unit is coupled between the corresponding first driving voltage and the operational amplifier for comparing the first driving voltage with the second driving voltage and outputting the overdriving voltage to the positive input terminal of the operational amplifier.

33. The source driver according to claim 32, wherein if the first driving voltage is greater than the second driving voltage, the overdriving voltage is greater than the first driving voltage;

if the first driving voltage is less than the second driving voltage, the overdriving voltage is less than the first driving voltage;

if the first driving voltage is equal to the second driving voltage, the overdriving voltage is equal to the first driving voltage.

34. The source driver according to claim 33, wherein the overdriving unit comprises:

a voltage detector, used for comparing the first driving voltage with the second driving voltage and outputting a voltage-increasing signal and a voltage-decreasing signal;

a control unit, coupled to the voltage detector and outputting a control signal according to the voltage-increasing signal and the voltage-decreasing signal; and

a voltage-regulating circuit, coupled to the control unit and regulating the voltage level of the overdriving voltage according to the control signal output from the control unit.

35. The source driver according to claim 34, wherein the voltage detector comprises:

a first PMOS transistor, being serially connected to a first NMOS transistor, and the first PMOS transistor and the first NMOS transistor are coupled between a first operation voltage and a first current source, wherein the gate of the first NMOS transistor is coupled to the first driving voltage;

a second PMOS transistor, being serially connected to a second NMOS transistor, and the second PMOS and the second NMOS transistor are coupled between the first operation voltage and the first current source, wherein the gate of the second NMOS transistor is coupled to the second driving voltage, the gate of the second PMOS transistor is coupled to the gate of the first PMOS transistor and the gate of the second PMOS transistor is coupled to the common node of the second PMOS transistor and the second NMOS transistor;

a second current source, being serially connected to a third NMOS transistor, and the second current source and the third NMOS transistor are coupled between the first operation voltage and a second operation voltage, wherein the gate of the third NMOS transistor is coupled to the common node of the first PMOS transistor and the first NMOS transistor, and the common node of the second current source and the third NMOS transistor outputs the voltage-decreasing signal; and

a third PMOS transistor, being serially connected to a third current source, and the third PMOS transistor and the third current source are coupled between the first operation voltage and the second operation voltage, wherein the gate of the third PMOS transistor is coupled to the common node of the first PMOS transistor and the first NMOS transistor, and the common node of the third PMOS transistor and the third current source outputs the voltage-increasing signal.

36. The source driver according to claim 34, wherein the voltage detector comprises:

a first PMOS transistor, being serially connected to a first NMOS transistor, and the first PMOS transistor and the first NMOS transistor are coupled between a first current source and a second operation voltage, wherein the gate of the first PMOS transistor is coupled to the first driving voltage;

a second PMOS transistor, being serially connected to a second NMOS transistor, and the second PMOS transistor and the second NMOS transistor are coupled between the first current source and the second operation voltage, wherein the gate of the second PMOS transistor is coupled to the second driving voltage, the gate of the second NMOS transistor is coupled to the gate of the first NMOS transistor and the gate of the second NMOS transistor is coupled to the common node of the second PMOS transistor and the second NMOS transistor;

a second current source, being serially connected to a third NMOS transistor, and the second current source and the third NMOS transistor are coupled between a first operation voltage and the second operation voltage, wherein the gate of the third NMOS transistor is coupled to the common node of the first PMOS transistor and the first NMOS transistor, and the common node of the second current source and the third NMOS transistor outputs the voltage-decreasing signal; and

a third PMOS transistor, being serially connected to a third current source, and the third PMOS transistor and the third current source are coupled between the first operation voltage and the second operation voltage, wherein the gate of the third PMOS transistor is coupled to the common node of the first PMOS transistor and the first NMOS transistor, and the common node of the third PMOS transistor and the third current source outputs the voltage-increasing signal.

37. The source driver according to claim 34, wherein the voltage detector comprises:

a first NMOS transistor, wherein both the gate of the first NMOS transistor and the gate of a first PMOS transistor are coupled to the second driving voltage;

a second NMOS transistor, wherein both the gate of the second NMOS transistor and the gate of a second PMOS transistor are coupled to the first driving voltage;

a first current source, coupled to the source of the first PMOS transistor and the source of the second PMOS transistor;

a second current source, coupled to the source of the first NMOS transistor and the source of the second NMOS transistor;

a third PMOS transistor, coupled between a first operation voltage and the drain of the first NMOS transistor;

a fourth PMOS transistor, coupled between the first operation voltage and the drain of the second NMOS transistor, wherein both the gate of the fourth PMOS transistor and the gate of the third PMOS transistor are coupled to a first bias voltage;

a fifth PMOS transistor, wherein the source of the fifth PMOS transistor is coupled to the drain of the third PMOS transistor;

a sixth PMOS transistor, wherein the source of the sixth PMOS transistor is coupled to the drain of the fourth PMOS transistor, and both the gate of the sixth PMOS transistor and the gate of the fifth PMOS transistor are coupled to a second bias voltage;

a third NMOS transistor, wherein the drain of the third NMOS transistor is coupled to the drain of the fifth PMOS transistor, and the source of the third NMOS transistor is coupled to the drain of the first PMOS transistor;

a fourth NMOS transistor, wherein the drain of the fourth NMOS transistor is coupled to the drain of the sixth PMOS transistor, both the gate of the fourth NMOS transistor and the gate of the third NMOS transistor are coupled to a third bias voltage, and the source of the fourth NMOS transistor is coupled to the drain of the second PMOS transistor;

a fifth NMOS transistor, coupled between the source of the third NMOS transistor and a second operation voltage, wherein the gate of the fifth NMOS transistor is coupled to the drain of the third NMOS transistor;

a sixth NMOS transistor, coupled between the source of the fourth NMOS transistor and the second operation voltage, wherein the gate of the sixth NMOS transistor is coupled to the gate of the fifth NMOS transistor;

a seventh NMOS transistor, coupled between a third current source and the second operation voltage, wherein the gate of the seventh NMOS transistor is coupled to the common node of the sixth PMOS transistor and the fourth NMOS transistor;

a seventh PMOS transistor, coupled between the first operation voltage and a fourth current source, wherein the gate of the seventh PMOS transistor is coupled to the common node of the sixth PMOS transistor and the fourth NMOS transistor;

wherein the common node of the seventh NMOS transistor and the third current source outputs the voltage-decreasing signal, while the common node of the seventh PMOS transistor and the fourth current source outputs the voltage-increasing signal.

38. The source driver according to claim 34, wherein the operational amplifier comprises a differential amplifier and an output-stage circuit, the differential amplifier outputs a differential signal to the output-stage circuit according to the signals received by the positive input terminal and the negative input terminal, and the voltage detector comprises:

an NMOS transistor, coupled between a first current source and a second operation voltage, wherein the gate of the NMOS transistor is coupled to the output terminal of the differential amplifier; and

a PMOS transistor, coupled between a first operation voltage and a second current source, wherein the gate of the PMOS transistor is coupled to the output terminal of the differential amplifier;

wherein the common node of the NMOS transistor and the first current source outputs the voltage-decreasing signal, while the common node of the PMOS transistor and the second current source outputs the voltage-increasing signal.

39. The source driver according to claim 34, wherein the control unit outputs a charging signal, a first path signal, a second path signal and a restoration signal for regulating the output of the voltage-regulating circuit, and the control unit comprises:

a clock-regulating circuit, outputting the charging signal and a reference signal according to a clock signal;

a first control circuit, outputting the first path signal according to the voltage-increasing signal and the reference signal;

a second control circuit, outputting the second path signal according to the voltage-decreasing signal and the reference signal; and

a restoration circuit, outputting the restoration signal according to the voltage-increasing signal, the voltage-decreasing signal and the reference signal.

40. The source driver according to claim 39, wherein the clock-regulating circuit comprises:

a delay circuit, used for delaying the clock signal and outputting a delayed clock signal;

an NOR gate, coupled to the delay circuit and outputting the reference signal according to the delayed clock signal and the clock signal; and

an NAND gate, coupled to the delay circuit and outputting the charging signal via an inverter according to the delayed clock signal and the clock signal.

41. The source driver according to claim 40, wherein the delay circuit comprises an even number of inverters.

42. The source driver according to claim 39, wherein the first control circuit comprises:

an NAND gate, wherein an input terminal of the NAND gate is coupled to the voltage-increasing signal, while another input terminal of the NAND gate is coupled to the reference signal; and

an inverter, wherein the input terminal of the inverter is coupled to the output terminal of the NAND gate and the inverter outputs the first path signal.

43. The source driver according to claim 39, wherein the second control circuit comprises:

a first inverter, wherein the input terminal of the first inverter is coupled to the voltage-decreasing signal;

an NAND gate, wherein an input terminal of the NAND gate is coupled to the output terminal of the first inverter, while another input terminal of the NAND gate is coupled to the reference signal; and

a second inverter, wherein the input terminal of the second inverter is coupled to the output terminal of the NAND gate and the second inverter outputs the second path signal.

44. The source driver according to claim 39, wherein the restoration circuit comprises:

a first inverter, wherein the input terminal of the first inverter is coupled to the voltage-increasing signal;

an NAND gate, having three input terminals coupled to the output terminal of the first inverter, the voltage-decreasing signal and the reference signal, respectively; and

a second inverter, wherein the input terminal of the second inverter is coupled to the output terminal of the NAND gate and the second inverter outputs the restoration signal.

45. The source driver according to claim 39, wherein the voltage-regulating circuit comprises:

a capacitor, having a first terminal and a second terminal;

a first switch, coupled between a charging voltage and the first terminal of the capacitor;

a second switch, coupled between the second terminal of the capacitor and a ground terminal;

a third switch, coupled between the second terminal of the capacitor and the first driving voltage;

a fourth switch, coupled between the first terminal of the capacitor and the positive input terminal of the operational amplifier;

a fifth switch, coupled between the first driving voltage and the first terminal of the capacitor;

a sixth switch, coupled between the second terminal of the capacitor and the positive input terminal of the operational amplifier; and

a seventh switch, coupled between the positive input terminal of the operational amplifier and the first driving voltage;

wherein if the charging signal is enabled, the first switch and the second switch are on;

if the first path signal is enabled, the third switch and the fourth switch are on;

if the second path signal is enabled, the fifth switch and the sixth switch are on;

if the restoration signal is enabled, the seventh switch is on.

46. The source driver according to claim 45, wherein the charging signal is enabled during a charging duration;

if the first driving voltage is greater than the second driving voltage, the first path signal is enabled during an overdriving duration;

if the first driving voltage is less than the second driving voltage, the second path signal is enabled during the overdriving duration;

the overdriving duration is after the charging duration, and if the restoration signal is enabled, the overdriving voltage is equal to the first driving voltage.

47. The source driver according to claim 46, wherein after the overdriving duration, the restoration signal is enabled during a restoration duration.

48. The source driver according to claim 45, wherein the charging signal is enabled during a charging duration;

if the charging signal is enabled, the seventh switch is on;

if the first driving voltage is greater than the second driving voltage, the first path signal is enabled during a overdriving duration;

if the first driving voltage is less than the second driving voltage, the second path signal is enabled during the overdriving duration;

the overdriving duration is after the charging duration.

49. The source driver according to claim 48, wherein after the overdriving duration, the restoration signal is enabled during a restoration duration, and if the restoration signal is enabled, the first switch and the second switch are either on or off.

50. The source driver according to claim 39, wherein when the charging signal is logic high, the charging signal is enabled;

when the first path signal is logic high, the first path signal is enabled;

when the second path signal is logic high, the second path signal is enabled;

when the restoration signal is logic high, the restoration signal is enabled.

51. The source driver according to claim 34, wherein the control unit outputs a first path signal, a second path signal and a restoration signal for regulating the output of the voltage-regulating circuit, and the control unit comprises:

a first inverter, used for inverting the voltage-increasing signal and outputting an inverted voltage-increasing signal;

an AND gate, used for generating the restoration signal according to the voltage-decreasing signal and the inverted voltage-increasing signal; and

a second inverter, used for inverting the voltage-decreasing signal and outputting the second path signal;

wherein the control unit directly outputs the first path signal according to the voltage-increasing signal.

52. The source driver according to claim 51, wherein the voltage-regulating circuit comprises:

a capacitor, having a first terminal and a second terminal;

a first switch, coupled between a charging voltage and the first terminal of the capacitor;

a second switch, coupled between the second terminal of the capacitor and a ground terminal;

a third switch, coupled between the second terminal of the capacitor and the first driving voltage;

a fourth switch, coupled between the first terminal of the capacitor and the positive input terminal of the operational amplifier;

a fifth switch, coupled between the first driving voltage and the first terminal of the capacitor;

a sixth switch, coupled between the second terminal of the capacitor and the positive input terminal of the operational amplifier; and

a seventh switch, coupled between the positive input terminal of the operational amplifier and the first driving voltage;

wherein if the first path signal is enabled, the third switch and the fourth switch are on;

if the second path signal is enabled, the fifth switch and the sixth switch are on;

if the restoration signal is enabled, the first switch, the second switch and the seventh switch are on.

53. The source driver according to claim 52, wherein if the first driving voltage is greater than the second driving voltage, the first path signal is enabled during an overdriving duration;

if the first driving voltage is less than the second driving voltage, the second path signal is enabled during the overdriving duration.

54. The source driver according to claim 53, wherein after the overdriving duration, the restoration signal is enabled during a restoration duration.

55. The source driver according to claim 51, wherein the voltage-regulating circuit comprises:

a first resistor, coupled between a first current source and the first driving voltage, wherein another terminal of the first current source is coupled to a first operation voltage;

a second resistor, coupled between the first driving voltage and a second current source, wherein another terminal of the second current source is coupled to a second operation voltage;

a first switch, wherein a terminal of the first switch is coupled to the common node of the first resistor and the first current source, while another terminal of the first switch is coupled to the positive input terminal of the operational amplifier;

a second switch, wherein a terminal of the second switch is coupled to the common node of the second resistor and the second current source, while another terminal of the second switch is coupled to the positive input terminal of the operational amplifier; and

a third switch, coupled between the positive input terminal of the operational amplifier and the first driving voltage;

wherein if the first path signal is enabled, the first switch is on;

if the second path signal is enabled, the second switch is on;

if the restoration signal is enabled, the third switch is on.

56. The source driver according to claim 51, wherein when the inverted voltage-decreasing signal is logic high, the second path signal is enabled;

when the voltage-increasing signal is logic high, the first path signal is enabled;

when the restoration signal is logic high, the restoration signal is enabled.

57. The source driver according to claim 55, wherein the first operation voltage is greater than or equal to a system operation voltage.

58. The source driver according to claim 55, wherein the second operation voltage is less than or equal to a ground voltage.

59. The source driver according to claim 34, wherein if the first driving voltage is greater than the second driving voltage, the voltage-increasing signal is logic high and the voltage-decreasing signal is logic high.

60. The source driver according to claim 34, wherein if the first driving voltage is less than the second driving voltage, the voltage-increasing signal is logic low and the voltage-decreasing signal is logic high.

61. The source driver according to claim 34, wherein if the input voltage is equal to the output voltage, the voltage-increasing signal is logic low and the voltage-decreasing signal is logic high.

62. The source driver according to claim 30, wherein the driving unit comprises:

a shift latch unit, used for latching the display signal and outputting a digital driving signal;

a level shifter, coupled to the shift latch unit for regulating the voltage level of the digital driving signal and outputting the regulated digital driving signal;

a digital-to-analog converter, coupled to the level shifter and generating the first driving voltages according to the digital driving signal output from the level shifter.

63. The source driver according to claim 62, wherein the shift latch unit comprises:

a shift register, used for outputting a shift signal; and

a latch unit, coupled to the shift register for latching the display signal according to the shift signal and outputting the digital driving signal.

64. The source driver according to claim 62, wherein the latch unit comprises:

a first latch, coupled to the shift register for latching the display signal step by step according to the shift signal; and

a second latch, coupled to the first latch for outputting the digital driving signal according to the latch result of the first latch.