Crystal oscillator emulator

• US 20080042767A1
• Filed: 04/03/2007
• Published: 02/21/2008
• Est. Priority Date: 10/15/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Sehat Sutardja
• Inventors: Sutardja, Sehat
• Granted Patent: US 7,760,036 B2
• Time in Patent Office: Days
• US Class Current: 331/176
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/166 Material
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 : Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/30 : with frequency-determining element being electromechanical resonator
• CPC Class Codes: H03L 1/026 : by using a memory for digitally storing correction values H03L1/025 takes precedence
• CPC Class Codes: H03L 1/027 : by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/substract logic circuit H03L1/023, H03L1/026 take precedence
• CPC Class Codes: H03L 5/00 : Automatic control of voltage, current, or power
• CPC Class Codes: H03L 7/08 : Details of the phase-locked loop
• CPC Class Codes: H03L 7/0802 : the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/0891 : the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/197 : a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/1974 : for fractional frequency division
• CPC Class Codes: H03L 7/1976 : using a phase accumulator for controlling the counter or frequency divider

Abstract

An integrated circuit comprises a film bulk acoustic resonator (FBAR) circuit that generates a reference frequency. A temperature sensor senses a temperature of the integrated circuit. Memory stores calibration parameters and selects at least one of the calibration parameters as a function of the sensed temperature. A phase locked loop module receives the reference signal, comprises a feedback loop having a feedback loop parameter and selectively adjusts the feedback loop parameter based on the at least one of the calibration parameters.

Claims

1. An integrated circuit comprising:

a film bulk acoustic resonator (FBAR) circuit that generates a reference frequency;

a temperature sensor that senses a temperature of said integrated circuit;

memory that stores calibration parameters and that selects at least one of said calibration parameters as a function of said sensed temperature; and

a phase locked loop module that receives said reference signal, that comprises a feedback loop having a feedback loop parameter and that selectively adjusts said feedback loop parameter based on said at least one of said calibration parameters.

2. The integrated circuit of claim 1 wherein said phase locked loop module comprises a fractional phase locked loop module and said feedback loop parameter includes a ratio of a scaling factor.

3. The integrated circuit of claim 2 wherein said fractional phase locked loop module comprises:

a phase frequency detector module that communicates with said FBAR circuit and that receives said reference frequency; and

a charge pump module that communicates with said phase frequency detector module.

4. The integrated circuit of claim 3 further comprising:

a voltage controlled oscillator that communicates with said charge pump module and that generates an output frequency; and

a scaling module that communicates with said voltage controlled oscillator and said phase frequency detector module, that selectively divides said output frequency by first and second scaling factors and that selectively adjusts a ratio of said first and second scaling factors based on said at least one of said calibration parameters.

5. The integrated circuit of claim 4, wherein said first and second scaling factors are divisors equal to N and N+1, respectively, and wherein N is an integer greater than zero.

6. The integrated circuit of claim 1 wherein said phase locked loop module comprises a Delta Sigma fractional phase locked loop module and said feedback loop parameter includes modulation of a scaling divisor.

7. The integrated circuit of claim 6 wherein said Delta Sigma fractional phase locked loop module comprises:

a phase frequency detector module that communicates with said FBAR circuit and that receives said reference frequency; and

a charge pump module that communicates with said phase frequency detector module.

8. The integrated circuit of claim 7 further comprising:

a voltage controlled oscillator that communicates with said charge pump module and that generates an output frequency;

a scaling module that communicates with said voltage controlled oscillator and said phase frequency detector module and that selectively divides said output frequency by first and second scaling factors; and

a Sigma Delta modulator that adjusts modulation of said scaling module between said first and second scaling factors based on said at least one of said calibration parameters.

9. The integrated circuit of claim 8 wherein said first and second scaling factors are divisors equal to N and N+1, respectively, and where N is an integer greater than zero.

10. The integrated circuit of claim 1 wherein said FBAR circuit comprises:

a semiconductor oscillator that generates resonator drive signal having a drive frequency; and

a FBAR that receives said resonator drive signal.

11. An integrated circuit comprising:

film bulk acoustic resonator (FBAR) means for generating a reference frequency;

temperature sensing means for sensing a temperature of said integrated circuit;

storing means for storing calibration parameters and for selecting at least one of said calibration parameters as a function of said sensed temperature; and

phase locked loop means for receiving said reference signal, for providing a feedback loop having a feedback loop parameter and for selectively adjusting said feedback loop parameter based on said at least one of said calibration parameters.

12. The integrated circuit of claim 11 wherein said phase locked loop means comprises a fractional phase locked loop and said feedback loop parameter includes a ratio of a scaling factor.

13. The integrated circuit of claim 12 wherein said fractional phase locked loop comprises:

phase frequency detector means that communicates with said FBAR means for receiving said reference frequency; and

charge pump means for communicating with said phase frequency detector means.

14. The integrated circuit of claim 13 further comprising:

voltage controlled oscillating means that communicates with said charge pump means for generating an output frequency; and

scaling means that communicates with said voltage controlled oscillating means and said phase frequency detector means, for selectively dividing said output frequency by first and second scaling factors and for selectively adjusting a ratio of said first and second scaling factors based on said at least one of said calibration parameters.

15. The integrated circuit of claim 14, wherein said first and second scaling factors are divisors equal to N and N+1, respectively, and wherein N is an integer greater than zero.

16. The integrated circuit of claim 11 wherein said phase locked loop means comprises a Delta Sigma fractional phase locked loop and said feedback loop parameter includes modulation of a scaling divisor.

17. The integrated circuit of claim 16 wherein said Delta Sigma fractional phase locked loop comprises:

phase frequency detector means that communicates with said FBAR means for receiving said reference frequency;

charge pump means for communicating with said phase frequency detector means; and

voltage controlled oscillating means that communicates with said charge pump means for generating an output frequency.

18. The integrated circuit of claim 17 further comprising:

scaling means that communicates with said voltage controlled oscillating means and said phase frequency detector means for selectively dividing said output frequency by first and second scaling factors; and

Sigma Delta modulating means for adjusting modulation of said scaling means between said first and second scaling factors based on said at least one of said calibration parameters.

19. The integrated circuit of claim 18 wherein said first and second scaling factors are divisors equal to N and N+1, respectively, and where N is an integer greater than zero.

20. The integrated circuit of claim 11 wherein said FBAR means comprises:

semiconductor oscillating means for generating resonator drive signal having a drive frequency; and

FBAR resonating means for receiving said resonator drive signal.

21. A method comprising:

providing a film bulk acoustic resonator (FBAR) that generates a reference frequency;

sensing a temperature of said integrated circuit;

storing calibration parameters;

selecting at least one of said calibration parameters as a function of said sensed temperature;

providing a phase locked loop that receives said reference signal and that comprises a feedback loop having a feedback loop parameter; and

selectively adjusting said feedback loop parameter based on said at least one of said calibration parameters.

22. The method of claim 21 wherein said phase locked loop comprises a fractional phase locked loop and said feedback loop parameter includes a ratio of a scaling factor.

23. The method of claim 22 further comprising:

providing a phase frequency detector that communicates with said FBAR and that receives said reference frequency; and

providing a charge pump that communicates with said phase frequency detector.

24. The method of claim 23 further comprising:

generating an output frequency; and

selectively dividing said output frequency by first and second scaling factors; and

selectively adjusting a ratio of said first and second scaling factors based on said at least one of said calibration parameters.

25. The method of claim 24, wherein said first and second scaling factors are divisors equal to N and N+1, respectively, and wherein N is an integer greater than zero.

26. The method of claim 21 wherein said phase locked loop comprises a Delta Sigma fractional phase locked loop and said feedback loop parameter includes modulation of a scaling divisor.

27. The method of claim 26 further comprising:

providing a phase frequency detector that communicates with said FBAR and that receives said reference frequency; and

providing a charge pump module that communicates with said phase frequency detector.

28. The method of claim 27 further comprising:

generating an output frequency;

selectively dividing said output frequency by first and second scaling factors; and

adjusting modulation between said first and second scaling factors based on said at least one of said calibration parameters.

29. The method of claim 28 wherein said first and second scaling factors are divisors equal to N and N+1, respectively, and where N is an integer greater than zero.