Circuits and Methods for Generating a Common Voltage

• US 20080042958A1
• Filed: 05/07/2007
• Published: 02/21/2008
• Est. Priority Date: 05/12/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Kyu-Young
• Granted Patent: US 7,791,580 B2
• Time in Patent Office: Days
• US Class Current: 345/94
• CPC Class Codes: G09G 2320/0204 Compensation of DC component across the pixels in flat panels
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A circuit and a method for generating a common voltage, and a liquid crystal display (LCD) device including the circuit for generating a common voltage. Chip size and accumulated offset voltage of a liquid crystal display (LCD) may be reduced. The circuit for generating a common voltage includes a digital logic calculator, an input reference voltage generator, and a buffer unit. Prior to the generation of the common voltage, the digital logic calculator sets an input reference voltage corresponding to a target voltage.

Claims

1. A method of generating a common voltage comprising:

setting a first control register and an amplitude control register to a first target voltage of a common voltage and a target amplitude of the common voltage, respectively;

setting a second control register to a second target voltage of the common voltage based on the first target voltage and the target amplitude;

generating a first input reference voltage and a second input reference voltage corresponding to the values of the first and second control registers, respectively; and

outputting a first common voltage and a second common voltage by receiving the first and second input reference voltages, respectively.

2. The method of claim 1, wherein calculating the value the second control register is set to is performed by a digital logic calculator.

3. The method of claim 2, wherein the first control register is an n-bit register, the second control register is an L-bit register, and the amplitude control register is an m-bit register, wherein n, L, m are positive integers.

4. The method of claim 3, wherein the first target voltage corresponds to one of Va, Va+Vs, Va+2Vs, . . . , or Va+(2ⁿ−

1)Vs according to a bit value of the first control register.

5. The method of claim 3, wherein the target amplitude corresponds to one of Vb, Vb+Vs, Vb−

2Vs, . . . , or Vb+(2^m−

1)Vs according to a bit value of the amplitude control register.

6. The method of claim 3, wherein the second target voltage corresponds to one of Va+(2ⁿ−

1)Vs−

Vb, Va+(2ⁿ−

2)Vs−

Vb, . . . , or Va+(2^m−

1)Vs−

Vb according to a bit value of die second control register.

7. The method of claim 1, wherein the first common voltage is outputted by an operational amplifier (op-amp) having a gain of a+1, wherein a is a positive integer.

8. The method of claim 1, wherein the second common voltage is outputted by an op-amp having a gain of 1 and an op-amp having a gain of −

b that are cascade-coupled with each other, wherein b is a positive integer.

9. The method of claim 7, wherein the first common voltage is outputted as a high common voltage.

10. The method of claim 8, wherein the second common voltage is outputted as a low common voltage.

11. A circuit for generating a common voltage comprising:

a digital logic calculator configured to output a value of a second control register that is set to a second target voltage of a common voltage by receiving a value of an amplitude control register that is set to a target amplitude of the common voltage;

an input reference voltage generator configured to generate a first input reference voltage and a second input reference voltage by receiving a value of a first control register that is set to a first target voltage of the common voltage and the value of the second control register; and

a buffer unit configured to output a first common voltage and a second common voltage by receiving the first input reference voltage and the second input reference voltage.

12. The circuit of claim 11, further comprising:

a common voltage driver configured to receive the first common voltage and the second common voltage and provide the first common voltage and the second common voltage to a common electrode.

13. The circuit of claim 11, wherein the digital logic calculator calculates the value of the amplitude control register and the value of the first control register.

14. The circuit of claim 13, wherein the first control register is an n-bit register, the second control register is an L-bit register, and the amplitude control register is an m-bit register, wherein n, L, m are positive integers.

15. The circuit, of claim 14, wherein the first target voltage corresponds to one of Va, Va+Vs, Va+2Vs, . . . , or Va+(2ⁿ−

1)Vs according to a bit value of the first control register.

16. The circuit of claim 14, wherein the target amplitude corresponds to one of Vb, Vb+Vs, Vb+2Vs, . . . , or Vb+(2^m−

1)Vs according to a bit value of the amplitude control register.

17. The circuit of claim 14, wherein the second target voltage corresponds to one of Va+(2ⁿ−

1)Vs−

Vb, Va+(2ⁿ−

2)Vs−

Vb, . . . , or Va+(2^m−

1)Vs−

Vb according to a bit value of the second control register.

18. The circuit of claim 12, wherein the buffer unit comprises:

a high buffer configured to output the first common voltage by receiving the first input reference voltage; and

a low buffer configured to output the second common voltage by receiving the second input reference voltage.

19. The circuit of claim 18, wherein the high buffer includes an op-amp having a gain of a+1, wherein a is a positive integer.

20. The circuit of claim 18, wherein the low buffer includes an op-amp having a gain of 1 and an op-amp having a gain of −

b, wherein b is a positive integer.

21. The circuit of claim 20, wherein the op-amp of the low buffer having a gain of 1 and the op-amp of the low buffer having a gain of −

b are cascade-coupled with each other.

22. The circuit of claim 18, wherein the first common voltage is outputted as a high common voltage and the second common voltage is outputted as a low common voltage.

23. A liquid crystal display (LCD) comprising:

a liquid crystal display panel coupled to a plurality of gate lines and data lines;

a gate driver configured to drive the gate lines of the liquid crystal display panel;

a source driver configured to drive the data lines of the liquid crystal display panel; and

a common voltage driver circuit configured to drive a common voltage that is applied to a common electrode of the liquid crystal display panel, the common voltage driver circuit comprising a common voltage generator and a common voltage driver receiving and providing the first common voltage and the second common voltage to the common electrode, the common voltage generator comprising;

a digital logic calculator outputting a value of a second control register that is set to a second target voltage of a common voltage by receiving a value of an amplitude control register that is set to a target amplitude of the common voltage;

an input reference voltage generator generating a first input reference voltage and a second input reference voltage by receiving a value of a first control register that is set to a first target voltage of the common voltage and the value of the second control register; and

a buffer unit outputting a first common voltage and a second common voltage by receiving the first input reference voltage and the second input reference voltage.

24. The LCD of claim 23, wherein the digital logic calculator calculates the value of the amplitude control register and the value of the first control register.