TIMER RESET CIRCUIT FOR OVERCURRENT PROTECTION OF SWITCHING POWER AMPLIFIER

• US 20080043391A1
• Filed: 08/17/2006
• Published: 02/21/2008
• Est. Priority Date: 08/17/2006
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation), Panasonic Semiconductor Asia Pte Limited (Panasonic Holdings Corporation)
• Inventors: WONG, Shiah Siew, SUN, Jing
• Application Number:
  US11/465,152
• Publication Number:
  US 20080043391A1
• Time in Patent Office: Days
• US Class Current: 361/59
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers

Abstract

A smart overcurrent protection circuit is introduced. In case of successive current due to certain malfunctions flows in power transistor of a switching circuit a control signal is activated to stop power transistor switching. When overcurrent condition is no longer satisfied, the switching circuit is still able to return to normal operation.

Claims

1. A method for allowing a switching circuit which has stopped switching at the output stage of said switching circuit due to an overcurrent condition or overcurrent conditions, to return to normal operation, when said overcurrent condition or overcurrent conditions are no longer satisfied, the method comprising:

activating a control signal to stop signal switching at said output stage of said switching circuit upon sensing said overcurrent condition or said overcurrent conditions; and

starting a timer circuit upon detecting the activation of said control signal; and

generating a reset signal from said timer circuit after said control signal is activated for a predetermined time period, to deactivate said control signal.

2. The method according to claim 1, wherein said switching circuit is a switching amplifier or a switching regulator or a system that uses a switching circuit.

3. The method according to claim 2, wherein said switching amplifier is in single ended load configuration or in bridge tied load configuration.

4. The method according to claim 1, wherein said control signal is a digital signal or an analog signal or a signal of certain form that functions to imply an overcurrent condition or overcurrent conditions have been detected.

5. The method according to claim 1, wherein said control signal is activated by a SR latch.

6. The method according to claim 1, wherein said timer circuit is a delay circuit or a circuit that causes signal delay for said predetermined time period.

7. The method according to claim 1, wherein said reset signal is activated by said timer circuit.

8. The method according to claim 1, wherein said reset signal is a digital signal or an analog signal or a signal of certain form that functions to imply said control signal has been activated for said predetermined time period.

9. The method according to claim 1, wherein said predetermined time period is determined by said timer circuit.

11. The apparatus according to claim 10, wherein said switching circuit is a switching amplifier or a switching regulator or or a system that uses a switching circuit.

12. The apparatus according to claim 11, wherein said switching amplifier is in single ended load configuration or in bridge tied load configuration.

10. An apparatus for allowing a switching circuit, which has stopped switching at the output stage of said switching circuit due to an overcurrent condition or overcurrent conditions, to return to normal operation, when said overcurrent condition or overcurrent conditions are no longer satisfied, the apparatus comprising:

a SR latch operative to activate a control signal to stop signal switching at said output stage of said switching circuit upon sensing said overcurrent condition or said overcurrent conditions; and

a timer circuit operative to activate a reset signal after said control signal is activated for a predetermined time period.

13. The apparatus according to claim 10, wherein said control signal is a digital signal or an analog signal or a signal of certain form that functions to imply an overcurrent condition or overcurrent conditions have been detected.

14. The apparatus according to claim 10, wherein said timer circuit is a delay circuit or any similar circuit that causes signal delay for a deliberate pre-determined time period.

15. The apparatus according to claim 10, wherein said reset signal is activated by said timer circuit.

16. The apparatus according to claim 10, wherein said reset signal is a digital signal or an analog signal or a signal of certain form that functions to imply said control signal has been activated for said predetermined time period.

17. The apparatus according to claim 10, wherein said predetermined time period is determined by said timer circuit.