Non-volatile memory with both single and multiple level cells

• US 20080043527A1
• Filed: 08/21/2006
• Published: 02/21/2008
• Est. Priority Date: 08/21/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Granted Patent: US 7,474,560 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed between and coupled to a select gate and a multiple level non-volatile memory cell. Various embodiments include structure, process, and operation and their applicability for memory devices and systems. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of single level non-volatile memory cells and a number of multiple level non-volatile memory cells, where a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell.

Claims

1. A memory array, comprising:

a number of single level non-volatile memory cells;

a number of multiple level non-volatile memory cells;

a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells; and

wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells.

2. The array of claim 1, wherein the multiple level non-volatile memory cells are comprised of a lower page and at least one upper page of data and the single level non-volatile memory cells are comprised of a single page of data.

3. The array of claim 2, wherein the first single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for the upper page of the first multiple level non-volatile memory cell and a lower resting voltage of the first select gate.

4. The array of claim 1, wherein the array includes a second select gate coupled in series to an opposite end of a number of multiple level non-volatile memory cells relative to the first select gate.

5. The array of claim 4, wherein the array includes a second single level non-volatile memory cell interposed between and coupled to the second select gate and a second multiple level non-volatile memory cell.

6. The array of claim 5, wherein the second single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for the upper page of the second multiple level non-volatile memory cell and a lower resting voltage of the second select gate.

7. The array of claim 1, wherein the array includes a number of single level memory cells and a number of multiple level non-volatile memory cells coupled in series.

8. The array of claim 7, wherein the array includes a NAND string.

9. A memory array, comprising:

a number of NAND strings of non-volatile memory cells;

a number of source select gates on a source side of a string;

a number of drain select gates on a drain side of a string; and

wherein the number of source select gates includes a number of source select gates individually coupled to a single level non-volatile memory cell, and the number of drain select gates includes a number of drain select gates individually coupled to a single level non-volatile memory cell; and

wherein the single level non-volatile memory cells individually coupled to the source select gates and the single level non-volatile memory cells individually coupled to the drain select gates are coupled to and separated by a continuous series of multiple level non-volatile memory cells.

10. The array of claim 9, wherein the array is comprised of a NAND architecture of flash memory cells.

11. The array of claim 9, wherein the single level non-volatile memory cells are comprised of a single page of data and the multiple level non-volatile memory cells are comprised of a lower page and an upper page of data and wherein each page enables two data input selections.

12. The array of claim 11, wherein the NAND string enables 128 data input selections.

13. The array of claim 12, wherein the 128 data input selections are enabled by a continuous series of 31 multiple level non-volatile memory cells coupled to a first single level non-volatile memory cell that is coupled to a source select gate, and a second single level non-volatile memory cell that is coupled to a drain select gate.

14. A memory device, comprising:

an array of non-volatile memory cells including a string of non-volatile memory cells;

circuitry for control and access to the array of non-volatile memory cells;

wherein the array of non-volatile memory cells includes;

a number of single level non-volatile memory cells;

a number of multiple level non-volatile memory cells;

a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells; and

wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells.

15. The memory device of claim 14, wherein the first single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for an upper page of the first multiple level non-volatile memory cell and a lower resting voltage of the first select gate.

16. The memory device of claim 14, wherein the array includes a second select gate coupled in series to an opposite end of a number of multiple level non-volatile memory cells relative to the first select gate.

17. The memory device of claim 16, wherein the array includes a second single level non-volatile memory cell interposed between and coupled to the second select gate and a second multiple level non-volatile memory cell.

18. The memory device of claim 17, wherein the second single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for the upper page of the second multiple level non-volatile memory cell and a lower resting voltage of the second select gate.

19. A memory module, comprising:

a number of contacts;

two or more memory devices, each having access lines selectively coupled to the number of contacts; and

wherein at least one of the memory devices includes;

an array of non-volatile memory cells including a string of non-volatile memory cells;

circuitry for control and access to the array of non-volatile memory cells;

wherein the array of non-volatile memory cells includes;

a number of NAND strings of non-volatile memory cells;

a number of source select gates on a source side of a string;

a number of drain select gates on a drain side of a string; and

wherein the number of source select gates includes a number of source select gates individually coupled to a single level non-volatile memory cell, and the number of drain select gates includes a number of drain select gates individually coupled to a single level non-volatile memory cell; and

wherein the single level non-volatile memory cells individually coupled to the source select gates and the single level non-volatile memory cells individually coupled to the drain select gates are coupled to and separated by a continuous series of multiple level non-volatile memory cells.

20. The memory module of claim 19, wherein 128 data input selections are enabled by a continuous series of 31 multiple level non-volatile memory cells coupled to a first single level non-volatile memory cell that is coupled to a source select gate, and a second single level non-volatile memory cell that is coupled to a drain select gate.

21. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device includes;

an array of non-volatile memory cells including a NAND string;

circuitry for control and access to the array of non-volatile memory cells; and

wherein the array of non-volatile memory cells includes;

no source select gate and no drain select gate being adjacent a multiple level non-volatile memory cell in the NAND string;

each select gate and each drain select gate being adjacent a single level non-volatile memory cell in the NAND string; and

no multiple level non-volatile memory cell being adjacent more than one single level non-volatile memory cell in the NAND string.

22. The electronic system of claim 21, wherein the array includes a plurality of serial NAND strings each coupled to a bit line and a plurality of rows of non-volatile memory cells.

23. A method of forming a memory array, comprising:

forming a number of series coupled non-volatile memory cells;

forming a number of series coupled select gates, wherein the series coupled select gates are coupled in series with the number of non-volatile memory cells; and

wherein forming the number of series coupled non-volatile memory cells includes forming a first single level non-volatile memory cell directly coupled to a first select gate and directly coupled to a first multiple level non-volatile memory cell;

wherein forming the number of series coupled non-volatile memory cells includes forming a second single level non-volatile memory cell directly coupled to a second select gate and directly coupled to a second multiple level non-volatile memory cell; and

wherein forming the number of series coupled non-volatile memory cells includes forming the first multiple level non-volatile memory cell and the second multiple level non-volatile memory cell directly coupled to at least one interposed multiple level non-volatile memory cell.

24. The method of claim 23, wherein forming a single level non-volatile memory cell includes forming a cell that stores a choice of two data input selections equaling one data bit and wherein forming a multiple level non-volatile memory cell includes forming a cell that stores a choice of four data input selections equaling two data bits.

25. The method of claim 24, wherein forming the number of series coupled non-volatile memory cells includes forming a number of NAND strings.

26. The method of claim 25, wherein forming each NAND string includes enabling 128 data input selections.

27. The method of claim 26, wherein enabling the 128 data input selections is done by forming 31 multiple level non-volatile memory cells coupled to the first single level non-volatile memory cell that is coupled to a source select gate and the second single level non-volatile memory cell that is coupled to a drain select gate.

28. The method of claim 25, wherein forming the number of series coupled non-volatile memory cells includes forming 31 multiple level non-volatile memory cells and two single level non-volatile memory cells in each NAND string.

29. The method of claim 23, wherein forming a single level non-volatile memory cell includes forming a cell that stores one data bit and wherein forming a multiple level non-volatile memory cell includes forming a cell that stores a plurality of data bits.

30. A method of forming a memory block, comprising adding a number of word lines to a string having a number of single level non-volatile memory cells and a number of multiple level memory cells for maintaining a previous memory block size.

31. The method of claim 30, wherein adding the number of word lines includes adding a number of non-volatile memory cells selected from single level non-volatile memory cells and multiple level memory cells.

32. The method of claim 31, wherein forming the memory block includes using one or more strings having a number of single level non-volatile memory cells and a number of multiple level memory cells.

33. The method of claim 32, wherein maintaining the previous memory block size includes maintaining a particular number selected from data input selection choices, memory bits, and pages associated with the previous memory block size.

34. The method of claim 33, wherein maintaining the previous memory block size includes maintaining the number of data input selection choices on a string at around 128, the number of memory bits on a string at around 64, and the number of pages in a memory block at around 128.

35. A method for operating a memory system, comprising:

applying a first select line potential to a source select gate and second select line potential to a drain select gate;

applying a first word line potential to a second non-volatile memory cell in a NAND string relative to a direction of the source gate and the drain gate that is closer, wherein the second non-volatile memory cell is a first multiple level non-volatile memory cell directly coupled to at least one additional multiple level non-volatile memory cell; and

applying a second word line potential to a first non-volatile memory cell in the NAND string, which is a single level non-volatile memory cell, wherein the second word line potential is lower than the first word line potential and greater than a potential of a directly coupled select gate.

36. The method of claim 35, wherein applying a potential includes applying a third word line potential to a number of unselected non-volatile memory cells in the NAND string.

37. A method of programming a memory array, comprising programming a single level memory cell adjacent a select gate to a programmed state when a next adjacent multiple level memory cell is in a programmed state.

38. The method of claim 37, wherein programming the single level memory cell includes reducing a probability of current leakage from the programmed multiple level memory cell to the select gate adjacent the single level memory cell.

39. A method for programming a NAND flash memory device comprising a memory array having a plurality of source select gates, a plurality of drain select gates, a plurality of single level non-volatile memory cells, and a plurality of multiple level non-volatile memory cells, the method comprising:

programming the memory array such that no source select gate and no drain select gate is adjacent a multiple level non-volatile memory cell in a NAND string;

programming the memory array such that each source select gate and each drain select gate is adjacent a single level non-volatile memory cell in the NAND string; and

programming the memory array such that no multiple level non-volatile memory cell is adjacent more than one single level non-volatile memory cell in the NAND string.

40. The method of claim 39, wherein programming the NAND flash memory device comprises programming a memory array having a plurality of serial NAND strings each coupled to a bit line and a plurality of rows of non-volatile memory cells.

41. The method of claim 39, wherein programming the NAND flash memory device includes controlling memory operations using a memory control circuit.

42. The method of claim 41, wherein controlling memory operations comprises using a state machine as the memory control circuit.